Title:  Hierarchical test generation for Open and Short circuit Defect Exposure: A Systematic Methodology

Committee:

Dr. Abhijit Chatterjee, ECE, Chair, Advisor

Dr. , Co-Advisor

Dr. Linda Milor, ECE

Dr. Saibal Mukhopadhyay, ECE

Dr. Suriyaprakash Natarajan, Intel

Dr. Adit Singh, Auburn

Abstract: This research is focused on the development of a hierarchical test generation methodology of intra-cell open and short manufacturing defects across a range of defect sizes in the digital standard cell libraries. In this research, we perform exhaustive SPICE simulations for the characterization and identification of input stimuli of open and short defects at the standard cell level. One of the key contributions of this research is the exposure of subtle open and short defects which escape the traditional stuck at and transition-delay fault testing and are detected by specific multi-bit change and multi-time frame test patterns. The SPICE simulation can be very time expensive and so, as the next key contribution of this research, we present fast test generation algorithms for both open and short defects based on observations from the SPICE simulation data and the principles of device physics such as charge sharing, voltage division, and Elmore delay model. Another key contribution is the application of the standard cell level tests to the circuit level tests. For this, we develop a SAT ATPG infrastructure which consists of interleaved combinations of launch on shift and launch on capture for the multi time frame test application. Overall, this research presents a bottom-up test generation approach with exposure of defects that escape traditional testing. Experimental results are presented on 45nm technology cell library for ISACAS85 and ISCAS89 benchmark circuits.