Title:  Reliability and Security of Compute-In-Memory Based Deep Neural Network Accelerators

Committee: 

Dr. Yu, Advisor   

Dr. Mukhopadhyay, Chair

Dr. Lim

Abstract: The proposed research aims to explore the reliability and security issues that existed in computing-in-memory (CIM) design for accelerating Deep Neural Network (DNN) algorithms. To protect the raw on-chip weights in CIM inference designs, we first aim at developing a secure SRAM-based XOR-CIM engine. A modified reverse secure sketch protocol is applied to enable on-chip authentication, and key processing for XOR-based stream cipher encrypted models.  Secondly, the research focuses on investigating the impact of non-idealities in CIM designs. We find that on-chip weights could be fine-tuned to compensate the process variations to recover the inference accuracy. Inspired by the necessary retraining, we also propose a PUF-like scheme against the weight cloning attack, which could maintain high accuracy on each chip instance while its performance will significantly degrade on other chip instances even with cloned weights. The future research will mainly focus on two topics: 1) explore other key factors that impact the design of compute-in-memory accelerators such as quantization methods 2) solve the reliability issues in CIM training process, especially for eNVM-based designs.