Title:  Building Efficient Tensor Accelerators for Sparse Andirregular Workloads

Committee: 

Dr. Krishna, Advisor      

Dr. Kim, Chair

Dr. Vuduc

Dr. Rajamanickam

Abstract: The objective of the proposed research is to create novel methodologies and architectures for building efficient sparse hardware accelerators that target machine learning and scientific workloads. Tensor kernels enable a vast amount of applications, including image classification and data analytic. One popular kernel that is often targeted for hardware acceleration is matrix multiplication. However, the dimensions, amount of sparsity and structure of each matrix operand varies across workloads. For example, in deep learning, tall-skinny matrices often occur because of the use of mini-batches and weight factorization. Additionally, the sparsity level of each matrix can span from 0% up to 99.99..% sparse across various workloads. Both the irregularity and sparsity have significant implications on the compute efficiency of current state-of-the-art accelerators. Many accelerators optimize for workloads of a certain size and sparsity level, but consequently, the accelerators will perform significantly worse for workloads of other sizes and sparsity levels. This is problematic for accelerators within HPC datacenters, as they are expected to run a wide range of workloads and adapt for future applications. The thesis proposes microarchitectures and techniques that maximize accelerator efficiency across workloads.