Title:  Machine Learning based Design and Optimization for High-Performance Microelectronic Packaging and Systems

Committee:

Dr. Madhavan Swaminathan, ECE, Chair , Advisor

Dr. Saibal Mukhopadhyay, ECE

Dr. Arijit Raychowdhury, ECE

Dr. Sung Kyu Lim, ECE

Dr. Surya Kalidindi, ME

Abstract: Semiconductor industry has seen a rapid advancement over the last two decades as the number of transistors in a functional chip increased based on Moore’s Law. When the increased transistor density is combined with techniques such as 3-D die stacking and advanced packaging through heterogeneous integration, it is possible dramatically increase the integration density and build high-performance electronic systems. However, these result in a significant increase in design complexity and raise new challenges related to design optimization, design space exploration (DSE) and uncertainty quantification (UQ). Optimization of such systems correspond to finding the minimum or maximum of a high-dimensional, non-convex function in the black-box setting where the function queries correspond to CPU intensive multi-physics simulations. Conventional methods either get stuck in a local optima, or require numerous system simulations that take impractical computational time and resources. For the problems related to DSE and UQ, an accurate data-based model of the system is often desired to run a comprehensive parametric analysis. Conventional techniques to derive such models either suffer from low accuracy due to high-dimensionality, high non-linearity or scarce data. To address these challenges, the first part of thesis develops new domain-specific single- and multi-objective Bayesian optimization based algorithms that are suited to packaging related problems and enable convergence to global optima in minimal number of system simulations. The second part of this thesis develops machine learning based models based on neural networks and Gaussian Processes to be used for DSE and UQ with the goal of learning the mapping from high-dimensional control parameters of the system to its performance metrics. The performance of the new methods developed in both parts are evaluated on design applications emerging in high-speed chip-to-chip signaling, power delivery, embedded passives for wireless power transfer and sub-THz wireless communication, and power modules for electric vehicles.