PhD Proposal by Amy Brummer

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THE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING   GEORGIA INSTITUTE OF TECHNOLOGY   Under the provisions of the regulations for the degree DOCTOR OF PHILOSOPHY on Wednesday, June 17, 2020 3:00 PM via   BlueJeans Video Conferencing https://bluejeans.com/522788248   will be held the   DISSERTATION PROPOSAL DEFENSE for   Amy Brummer   “Area-Selective Deposition of Gate Stack Materials for Fabrication of Nanowire Transistors”   Committee Members:   Prof. Eric Vogel, Advisor, MSE Prof. Mike Filler, Advisor, ChBE Prof. Asif Khan, ECE Prof. Mark Losego, MSE Prof. Natalie Stingelin, MSE/ChBE   Abstract:   This work aims to develop methods to support the distributed production of on-demand integrated circuits for high-performance flexible electronics. Conventional integrated circuit technology has made great strides over the past 50 years and today can produce very small integrated circuit (IC) chips with billions of transistors. However, IC fabrication is approaching the scaling limit for transistors and will eventually not be able to pack more power and functionality into smaller sized chips. And this billion-dollar industry limits process and product innovation simply due to the high costs involved in implementation of new techniques. But what if electronics fabrication could be a more dynamic and customizable process that could still manufacture at very large scales? By shifting the fabrication paradigm and embracing scalable, bottom-up fabrication techniques, fully formed high-performance nanowire transistors can be produced and interconnected with an adaptive printing technique for low-cost, large-area flexible electronics applications.   The objective of this work is to fabricate these nanowire transistors and understand how the material deposition and post-deposition processing will impact performance of the devices. A polymer masking material will be used to pattern dopant-modulated Si nanowires. This enables selective deposition of a high-κ dielectric and a metal electrode via atomic layer deposition (ALD) to form a gate stack around the transistor channel. The deposition of dielectric and metal films will be studied to understand how the selective ALD process impacts the electronic properties of the films. These selective deposition techniques will then be combined to form self-aligned MOS capacitors to study the influence of post-deposition annealing and interfacial layers on the device performance to develop an optimized materials system for the gate stack. Finally, the gate stack will be deposited on nanowires to form bottom-up field-effect transistors, and the formation of printed low-contact resistance interconnects between nanowire devices dispersed on a substrate will be investigated. This work will contribute to the fundamental understanding of how selective deposition techniques can affect electronic properties of thin films and how to further improve their performance for electronics applications. And if successful, these high-performance, bottom-up devices could be combined with dynamically printed interconnections to produce ICs without the use of photolithography or the wafer-based planar process.


  • Workflow Status: Published
  • Created By: Tatianna Richardson
  • Created: 06/02/2020
  • Modified By: Tatianna Richardson
  • Modified: 06/02/2020