Title:  Design, Modeling, Optimization, and Benchmarking of Interconnects and Scaling Technologies and their Impact on Circuit and System Level

Committee: 

Dr. Naeemi, Advisor      

Dr. Davis, Chair

Dr. Lim

Abstract:

The objective of the proposed research is focused on the future of integrated circuit (IC) scaling technologies at the device and back end of line (BEOL) level. This work includes high level modeling of the different technologies and quantifying the proposed performance gains on a circuit and system level. From the device side, this research will look at proposed scaling challenges and the future scaling drivers for the 7nm technology and beyond for more conventional charge-based devices. It’ll also look at the system performance of tunneling field effect transistors (TFET) and their potential as a beyond CMOS devices. Finally, this research will focus on BEOL scaling challenges and proposed technological advancements and quantify their potential impacts on a fully place and routed circuit.