PhD Defense by Chandrasekharan Nair

Event Details
  • Date/Time:
    • Tuesday May 14, 2019 - Wednesday May 15, 2019
      2:00 pm - 3:59 pm
  • Location: MaRC 201
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Summary Sentence: Modeling, Design, Materials, Processes and Reliability of Multi-layer Redistribution Wiring Layers on Glass Substrates for Next Generation of High-Performance Computing Applications

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Under the provisions of the regulations for the degree


on Tuesday, May 14, 2019

2:00 pm
in MaRC 201


will be held the





Chandrasekharan Nair


" Modeling, Design, Materials, Processes and Reliability of Multi-layer Redistribution Wiring Layers on Glass Substrates for Next Generation of High-Performance Computing Applications"


Committee Members:


Prof. Rao Tummala, Advisor, MSE

Prof. P. M. Raj, Florida International University

Prof. Preet Singh, MSE

Prof. Eric Vogel, MSE

Prof. Azad Naeemi, ECE




There has been tremendous research in driving the technologies for integrated circuit (IC) device scaling since the 1960s. The primary driver of device scaling, Moore’s Law, states that the number of transistors in an integrated circuit (IC) doubles every two years. This has resulted in steady increase in transistor density, and therefore increased computing and wireless performance at the device level. As IC device scaling is slowing down in recent times, new solutions are being undertaken to improve performance of the entire system. These ICs historically were integrated on to the package substrate and interconnected to each other through the printed wiring board. Since 2010s, heterogeneous integration of multiple ICs on to a package substrate has become one of the most popular solutions to improve system performance and miniaturization. This technique is employed in the form of 2.5D package architectures for high performance computing applications like in datacenters, gaming, and embedded fan-out package architectures for high end smartphones like in iPhone X, etc. Thus, package substrate has been a huge enabler to system scaling in terms of overall miniaturization, high bandwidth performance per watt of power consumed and high density of interconnections between heterogeneous dies to enable more operations per second.


The research proposed in this thesis work focuses on the critical redistribution layer (RDL) technology on the package substrate which is responsible for high density wiring between ICs. Current 2.5D silicon interposer package substrates focus on back end of line architectures with 1-2 micron RDL to interconnect GPU and HBM stacks. However, they face three challenges in terms of : (A) High RC delay RDL wiring connections slowing down the system performance, (B) Large body size substrates to interconnect more dies and improve system bandwidth performance and, (C) The coefficient of thermal expansion (CTE) mismatch between silicon (3 ppm/K) and printed wiring board (20 ppm/K) results in board level reliability failures, thereby requiring an additional package substrate (CTE ~ 10 ppm/K) to attach the silicon interposer to the board. Glass interposer is a promising alternative solution to this problem. The availability of glass in large panel forms and the tailorability of glass CTE resolves the latter two issues of silicon interposers. The polymer dielectric based RDL technology for panel platforms is still limited to 5-6 micron features and the proposed research focuses on scaling to 2 micron RDL in three target areas: (A) Modeling and Design for low RC delay, high bandwidth 2 micron polymer RDL, (B) Developing novel processes for fabrication of 2 micron RDL on panel platforms and, (C) Reliability assessment of the fabricated multi-layer 2 micron RDL.


The first target area addresses the need for low RC delay RDL and the approach of 2 micron width, high aspect ratio (2-4) copper traces seems promising to reduce RC delay. The current challenges with other panel platforms like organic substrates to scale to the required RDL I/O densities due to their dimensional instability will be addressed. The second area focuses on developing novel materials and processes for fabrication of high aspect ratio copper traces in terms of lithography for fine resolution patterning, seed layer removal for zero side-etch, scaling down microvia diameters to 2 micron and excellent adhesion of high aspect ratio copper traces to polymer dielectrics. The third and final area focuses on reliability assessment of 2 micron RDL with respect to electrical leakage failures between copper traces in polymer dielectrics and developing a model to predict such failures. The research also addresses the effect of different CTE polymer dielectrics on 2 micron diameter microvia reliability.

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Phd Defense
  • Created By: Tatianna Richardson
  • Workflow Status: Published
  • Created On: May 9, 2019 - 1:03pm
  • Last Updated: May 9, 2019 - 1:04pm