THE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING

GEORGIA INSTITUTE OF TECHNOLOGY

Under the provisions of the regulations for the degree

MASTER OF SCIENCE

on Thursday, April 20, 2017

2:00 - 3:00 PM
in MaRC 201

will be held the

MASTER’S THESIS DEFENSE

for

Vidya Jayaram

"Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip- and- board-level reliability"

Committee Members:

Prof. Rao Tummala, Advisor, MSE

Prof. Suresh Sitaraman, ME

Dr. Vanessa Smet, ECE

Abstract:

Transistor scaling, driven by Moore’s Law, has enabled the integration of billions of transistors on a single integrated chip (IC); thereby enabling rapid miniaturization of microprocessor devices such as smartphones, servers and personal computers. However, silicon integration following Moore's law is now reaching its limits due to increasing design complexity and cost, bringing the need for a new "System Scaling" approach for further miniaturization and performance improvements. The System-on-Package (SOP) approach, pioneered by Georgia Tech PRC, relies on co-integration of multiple electronic functions on a package substrate, as opposed to on-chip. Packaging, therefore, becomes key in enabling higher functional densities. An example of this new approach to system design is the recent trend of "split dies" where a large devices is broken down into smaller devices at finer I/O pitches that are interconnected on a substrate using high-density wiring. These advanced package architectures such as 2.5D interposer packages now rely on packaging to improve performance and miniaturize the system as a whole.

Silicon interposers are particularly attractive in such split-die applications due to their outstanding lithographic capability enabling high-density, high-speed die-to-die interconnections. Such 2.5D interposers tend to be fairly large with body sizes exceeding 30mmx40mm, bringing unprecedented board-level reliability challenges due to large mismatch in coefficients of thermal expansion (CTE) between silicon and mother boards. These challenges are typically addressed by introducing an additional organic BGA package between interposer and board to accommodate for the CTE mismatch and decrease in pitch. However, this degrades electrical performance with longer interconnection lengths, and adds to the overall cost.

Glass has emerged as an alternative substrate technology to overcome the shortcomings of silicon. Glass has been demonstrated to have superior electrical properties than silicon with lower losses and can accommodate high-density wiring owing to micron-scale lithographic design rules. Further, glass can be tailored for a wide CTE range of 3.3 to 9.8 ppm/K. This unique property brings design flexibility to address board-level reliability challenges and directly assemble large glass interposer packages to boards without the need for an intermediate organic package. 

The primary objective of this research is to model, design and demonstrate a large, 2.5D glass BGA package with 1) direct SMT-to-board interconnection; and 2) balanced chip- and- board-level reliability. The ultimate goal is to provide guidelines for the design of 2.5D glass BGA packages, optimizing the glass CTE to mitigate warpage and achieve system-level reliability, and subsequently the assembly process and sequence. 

Finite-element models were built to assess the reliability of 2.5D glass packages with direct SMT assembly to the board. The methodology for achieving balanced chip- and- board-level reliability was validated through focused modeling and experimental results for a single-chip package. Board-level reliability was recognized as the most critical challenge and enhanced by using innovative doped solder materials such as Indium’s Mn-doped SACmTM alloy and strain-relief mechanisms to give more design flexibility. Failure distribution analysis and optical characterization was performed to evaluate thermal cycling reliability. A process design approach was demonstrated for mitigating warpage induced by thermocompression bonding on ultra-thin, low- and- high-CTE substrates at I/O pitches below 50µm. By selecting optimum thermal profiles for mitigating chip-level assembly warpage, board-level assembly is enabled at larger package sizes, and system-level reliability is thereby enhanced.