SCS Lecture Series: Carlos T. Ortega Otero, "IBM TrueNorth: A 65mW, 1 Million Neuron Programmable Neurosynaptic Chip"

Event Details
  • Date/Time:
    • Friday October 7, 2016 - Saturday October 8, 2016
      2:00 pm - 2:59 pm
  • Location: Klaus Advance Computing Building (KACB), Room 1116 East and West
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Kenya Payton​


Summary Sentence: SCS Lecture from Carlos T. Ortega Otter, Research Scientist, IBM Research

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  • Carlos T. Ortega Otero Carlos T. Ortega Otero


Brain-inspired architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software.

With such aggressive design metrics and the TrueNorth architecture breaking path with prevailing architectures, it is clear that conventional CAD tools could not be used for the design. As a result, we developed a new design methodology that includes mixed asynchronous-synchronous circuits and a complete tool flow for building an event-driven, low-power neurosynaptic chip.

The TrueNorth chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. To reduce the system's communication energy, we have adapted existing application-agnostic very large-scale integration CAD placement tools for mapping logical neural networks to the physical neurosynaptic core locations on the TrueNorth chips.

With that, we have successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower power consumption than the same algorithms run on von Neumann architectures. The TrueNorth chip and its tool flow serve as building blocks for future cognitive systems, and give designers an opportunity to develop novel brain-inspired architectures and systems. 



Carlos Tadeo Ortega Otero joined IBM Research to work in the Brain-Inspired Computing group, and in particular on the SyNAPSE Project at IBM Almaden Research Center. Carlos is a Electrical and Computer Engineer whose research interest lie at the intersection of ultra-low power design, event-driven computation, and novel architecture design.

Carlos completed his PhD in Electrical and Computing Engineering, working with the Asynchronous VLSI group led by Professor Rajit Manohar at Cornell University.  At Cornell, he developed an Ultra-Low Energy RISC microcontroller that uses only 27pJ/instruction while operating at 50MHz. He also designed and tested ICs that range from complex FPGAs to custom logic — all test chips were fully functional on first-silicon.

Before joining IBM, Carlos worked as an R&D Engineer at St. Jude Medical in the cardiology division.  He developed the first-ever digital prototype for a MEMS based implantable sensor to detect blood pressure and cardiac output on patients with heart disease.


Please join us for our “TGIF” reception following the talk at 3 p.m. on the second floor of the Klaus commons area, overlooking the Atrium.

Light snacks and refreshments will be served.

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College of Computing, School of Computer Science

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Faculty/Staff, Public, Undergraduate students, Graduate students
Carlos T. Ortega Otero, SCS Lecture, School of Computer Science
  • Created By: Devin Young
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  • Created On: Oct 4, 2016 - 9:04am
  • Last Updated: Apr 13, 2017 - 5:14pm