PhD Defense by Corey Joiner
THE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING
GEORGIA INSTITUTE OF TECHNOLOGY
Under the provisions of the regulations for the degree
DOCTOR OF PHILOSOPHY
on Friday August 4, 2016
in Marcus 1117
will be held the
"Impact of Materials Disorder on Graphene Heterostructure Devices "
Prof. Eric Vogel, Advisor, MSE
Prof. Vladimir Tsukruk, MSE
Prof. Faisal Alamgir, MSE
Prof. Zhiqun Lin, MSE
Prof. Zhigang Jiang, PHYS
This work is focused on characterizing the impact of material based disorder on the properties of graphene based vertical tunneling heterostructures. The motivation and challenges for replacing silicon for low power digital electronics has been presented. The status of the research on graphene based digital electronics is critically reviewed. Scalable methods for synthesizing large area two dimensional materials including graphene, molybdenum disulfide, and hexagonal boron nitride are integrated into a complex CMOS fabrication process to investigate the impact of disorder on the properties of vertical graphene based heterostructures for low power digital electronics.
The foci for this study were 1) reducing the disorder in the form of contaminants and defect generation in the graphene structure introduced during the CMOS fabrication process 2) elucidating the impact of disorder on vertical tunneling in a graphene based vertical heterostructure 3) investigating the impact of sequential two dimensional material synthesis on the disorder and electrical performance of the fabricated heterostructures. The major findings of this work can be summarized by the following:
The CMOS fabrication process was found to introduce contaminants in the form of polymeric residues that reduced the lateral conduction of the graphene. Thermal decomposition of the residues resulted in the introduction of defects in the graphene. A chemical etching method utilizing a sacrificial titanium layer removed via HF etching effectively removed the contaminants without damaging the graphene.
Dielectric tunneling barriers were deposited by atomic layer deposition (ALD). The tunneling mechanism of the deposited barriers was found to be defect mediated tunneling which is undesirable for the graphene based heterostructures. By reducing the thickness of the tunneling barriers, direct tunneling became the dominant tunneling mechanism. By altering the tunneling barrier, the possibility of barrier engineering to tailor the electrical characteristics of the graphene heterostructure device was experimentally shown. Despite direct tunneling being the dominant tunneling mechanism for thin dielectric barriers, the electrical properties with ALD deposited dielectrics was found to be inadequate. Graphene of various domain sizes was used to assess the impact of disorder induced by the graphene on the heterostructure electrical properties. No change in the electrical properties was observed indicating the underlying substrate and interlayer dielectric are the limiting sources of disorder suppressing the heterostructure electrical properties.
Following recent reports utilizing exfoliated materials, two dimensional materials (molybdenum disulfide and hexagonal boron nitride) complimentary to graphene were utilized as tunneling dielectrics to further improve the device performance over conventional dielectric materials. The direct synthesis of complimentary two dimensional materials on graphene was shown to introduce defects into the graphene structure and to suppress the electrical properties of the graphene. Trapping of electrons due to the large number of trap states in the as synthesized molybdenum disulfide was shown to drastically suppress the tunneling current in the graphene vertical heterostructure compared to exfoliated materials.
Hexagonal boron nitride was used as a buffer layer between the graphene electrode and underlying SiO2 substrate to determine the impact of the substrate on the graphene heterostructure performance. A large area synthesized hexagonal boron nitride buffer layer was shown to improve the lateral conduction of the graphene. Contrary to reports of exfoliated materials, the introduction of a hexagonal boron nitride tunneling barrier was shown to reduce the mobility of the graphene due to increased scattering as a result of defects in the hexagonal boron nitride as well as contamination introduced during the transfer process. The lateral conductance of the graphene was shown to be improved in the graphene vertical heterostructure with a hexagonal boron nitride buffer layer, but was insufficient to improve the vertical tunneling of the heterostructure. Improved synthesis methods to reduce the intrinsic defects in the as synthesized hexagonal boron nitride is necessary to further improve the graphene heterostructure performance.
Overall, the research presented here provides important insights into the use of graphene based heterostructures for digital electronic applications. We provided methodology for integrating graphene into a CMOS fabrication process, suggest potential pathways for tailoring the device characteristics through barrier engineering, and demonstrate the current limitations of two dimensional heterostructures. We find the limiting factor to be the materials used in support of graphene.