Title:  Electrical Modeling, Design and Characterization of Tapered Through-package-vias in Glass Interposers for High-performance Applications

Committee:

Dr. Rao Tummala, ECE, Chair , Advisor

Dr. Andrew Peterson, ECE

Dr. Oliver Brand, ECE

Dr. Venkatesh Sundaram, PRC

Dr. Suresh Sitaraman, ME

Abstract: 

Three dimensional (3D) packaging technologies are being developed to address the escalating demand for data traffic at lowest power consumption, smallest form factors, and lowest cost. Glass has been proposed as a compelling alternative to silicon and the best packaging substrate for interposer, high-performance, and millimeter-wave applications. Through-package vias (TPVs) are a critical building block, particularly in 3D architectures. Typically, TPVs have a tapered shape as a result of high speed laser ablation and other commonly used via formation methods. Until now, the effects of taper on the electrical performance of TPVs in glass have yet to be reported. The objectives of this research were to model, design, and characterize tapered TPVs in glass interposers to provide design guidelines for TPVs by quantifying their impact on electrical performance. To achieve these objectives, three research tasks were carried out: 1) electrical modeling of TPVs by taking into account both geometric and material effects; 2) design of TPVs for minimum impedance discontinuity and crosstalk; 3) millimeter-wave characterization of TPVs to extract via parasitics.