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PhD Proposal Defense by Ting-Chia (Nathan) Huang

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Committee Members:

 

Prof. Rao R. Tummala (Advisor), MSE

Prof. Naresh Thadhani, MSE

Prof. Suresh K. Sitaraman, ME

Dr. Pulugurtha M. Raj, ECE

 

Abstract:

 

Emerging high-performance systems are driving the needs for advanced packaging solutions such as 3D ICs and 2.5D system integration with increasing performance and reliability requirements for off-chip interconnections. The research objectives are to design, develop and demonstrate novel, manufacturable, solder-based interconnections addressing the limitations of conventional Cu pillar technology in terms of pitch scalability, thermomechanical reliability, thermal stability and power-handling capability to extend the applicability of solders to next-generation high-performance packaging, at 20µm pitch and below. Pitch scaling with solders is hindered by three major technical challenges: a) reliability of ultra-short interconnections with reduced solder volume; b) shift from reflow to thermocompression bonding with limited assembly throughput and high-customized processes, yielding higher costs; c) non-controlled intermetallics formation leading to stress management issues and voiding. To address the aforementioned challenges, three research tasks were proposed and executed:

 

Task 1:

Novel metallic surface finishes without Ni are required in replacement of standard ENEPIG and ENIG finishes to achieve sub-10um interconnect pitch on high-density substrates without extraneous plating, and with improved high-frequency performance. A comprehensive study of the new electroless palladium autocatalytic gold (EPAG) finish supplied by Atotech GmBH was executed. The EPAG composition was optimized based on wettability testing, analysis of interfacial reactions, thermal cycling. Assemblies with the optimized EPAG composition exhibited a 3x improvement in fatigue life compared to assemblies with standard ENEPIG.

 

Task 2:

Amkor’s TC-NCP (thermocompression bonding with non-conductive paste) process has been demonstrated as one of the most promising process to achieve fine-pitch assembly at 40um pitch and below. Tool – material – process interactions have to be taken into account when designing thermocompression bonding heating and force profiles. Although Cu pillar TC bonding is an established technology on organic substrates and silicon interposers, there are no standard process guidelines and all process recipes are highly-customized given a test vehicle design, material set and bonder. This research constitutes the first demonstration of thermocompression assembly on ultra-thin glass substrates. Finite element modeling of the heat transfer in assembly, considering tool-package interactions, was first established and experimentally validated to provide guidelines for setup of assembly profiles. This methodology was also applied to design a high-throughput assembly process for metastable SLID bonding in task 3.

 

Task 3:

Further reduction of the solder volume to achieve finer pitches may give rise to severe interfacial stresses at the residual solder-to-intermetallics interfaces, drawing the limit of pitch scalability. Solid-liquid interdiffusion (SLID) bonding has been proposed and extensively researched as an alternative technology to form all-intermetallic joints with improved pitch scalability and power handling capability. However, the adoption of existing SLID technologies is limited due to reliability concerns, notably related to voiding, manufacturability and cost with relatively low-throughput processes. The proposed metastable SLID technology addresses these challenges by isolating the Cu6Sn5 metastable phase using Ni diffusion barrier layers, enabling full conversion into void-free intermetallics with highest interdiffusion rates. Metastable SLID was demonstrated at pitches down to 40um on glass, with superior shear strength of 90MPa, outstanding electromigration resistance at (is this the right number?) 5´105A/cm2, good thermal stability after 10x reflow cycle and excellent thermomechanical reliability, even with ultra-low-K devices.

Status

  • Workflow Status:Published
  • Created By:Jacquelyn Strickland
  • Created:05/04/2016
  • Modified By:Fletcher Moore
  • Modified:10/07/2016

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