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Logic Devices: Scaling for the Next 10 Years and Beyond

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Abstract: As our information infrastructure evolves through the next decade, data centers, smart mobile devices, and sensors will demand a variety of energy-efficient electronic systems that can satisfy a myriad of performance, form-factor, and cost needs. Thus, giving rise to challenges for performance, power, cost, and density scaling for nanoelectronics.  On the other hand, overcoming these new challenges will bring exciting innovations in process capability, material integration, device architectures, and system design. In this talk, we will examine some of the current logic scaling trends, review what are the possible paths forward for process technologies. To look at how IMEC contributes to the technology path finding, we will review some of the on-going IMEC Logic R&D activities on logic transistor innovations targeting 10nm, 7nm, 5nm, and beyond. This will include the processes for multi-gate devices beyond FinFETs, beyond-Si channel devices, and other emerging devices.

Biography: Aaron Thean, Ph.D., is the Vice President of Logic Process Technologies and Director of the Logic Devices R&D at IMEC. He directs device and process R&D ranging from ultra-scaled FinFETs to III-V/Ge Channels, emerging nano-device architectures, logic spintronics, and novel materials. Prior to joining IMEC, Aaron had held technology management positions at Qualcomm (San Diego, California) and IBM (East-Fishkill, New York). As an Engineering Manager at Qualcomm, he worked closely with process and design teams on 20nm technology. At IBM, he led the international process alliance team, as the 32nm/28nm device manager, to develop the first foundry-compatible Gate-First High-k Metal Gate bulk CMOS process for IBM and its technology partners. Aaron started his engineering/scientific career at Motorola/Freescale – Austin, Texas, where he became the manager of the Novel Devices Group.  As an alumni of the University of Illinois at Champaign-Urbana, where he received his B.Sc, M.Sc, and Ph.D degrees in Electrical Engineering. He has published over 50 papers in leading journals and conferences and holds more than 40 process technology patents.

Status

  • Workflow Status:Published
  • Created By:Christa Ernst
  • Created:07/28/2014
  • Modified By:Fletcher Moore
  • Modified:04/13/2017