TITLE: New dispatching approaches for WIP balancing and on-time delivery in semiconductor manufacturing
SPEAKER: Professor Oliver Rose
For a customer-oriented semiconductor wafer fab, low volume products such as development lots or customer samples are often more critical than high volume products with regard to cycle time and delivery reliability because of due date commitment. In this study, a global rule combining WIP balance and due date control is developed for a wafer fab with both low and high volume products. The purpose is to resolve the following two issues. how to balance WIP of high volume products with the due date cost of low volume products; and how to make the trade-off between on-time delivery and WIP balance for the low volume products.
In the second part of the talk, a priority matrix table is introduced to assign priority to lots considering both due date and workload information with the objective to keep lots going through the fab at the right pace to maintain WIP balance. Besides that, a WIP calibration method is proposed to recover WIP balance following unpredictable events such as tool failure. The simulation results demonstrate that the proposed priority matrix table achieves a better WIP balance than FIFO (first in first out) and ODD (operation due date), and the WIP calibration method is able to correct for the WIP imbalance.
- Workflow Status: Published
- Created By: Anita Race
- Created: 06/27/2013
- Modified By: Fletcher Moore
- Modified: 10/07/2016