Pragna Bhaskar
Advisor: Prof. Madhavan Swaminathan

Co-advisor: Prof. Mark D. Losego

will defend her doctoral thesis entitled,

Reliability assessment and demonstration of advanced ultra-low-k dielectric materials for advanced interposers

On

Friday, December 1 at 2:00 p.m.
Pettit Microelectronics Building 102 A&B

and

 Virtually via Zoom

https://gatech.zoom.us/j/97541898638?pwd=NTg5anh2SzAzUEIvZVVHREpINWhWQT09

Meeting ID: 975 4189 8638

Passcode: 136236

Committee

• Prof. Madhavan Swaminathan – School of Electrical and Computer Engineering and School of Materials Science and Engineering (Advisor)
• Prof. Mark D. Losego– School of Materials Science and Engineering (Co-advisor)
• Dr. Mohanalingam Kathaperumal – School of Electrical and Computer Engineering
• Prof. Hamid Garmestani – School of Materials Science and Engineering
• Prof. Preet Singh – School of Materials Science and Engineering         
             

Abstract
The number of connected devices in homes, cars and offices has increased and there is also an increase in advanced data processing algorithms. These have been enabled by artificial intelligence (AI) unprecedented need for ultra-high bandwidth computing. This need for ultra-high bandwidth is driving transistor density on single-chips. Moore’s Law had enabled the scaling and integration of compute, memory, and other functionalities on a single silicon chip by increasing transistor density on-chip at lower cost per transistor. This is known as the System on Chip (SoC) approach.

In the recent past, Moore’s law has slowed down and the cost of large SoCs has increased. There are two important reasons for this exponential increase in cost. The first reason is that the cost/mm2 of transistors has continued to increase due to increase in technology complexity. The second reason is that yields have reduced for larger SoCs as the limits of the reticle field are approached. One of the methods to address these requirements is by adopting Heterogeneous Integration. In this approach, separately manufactured dies are integrated onto an advanced interposer which provides better functionality and operating characteristics. These dies need to communicate with high bandwidth density at low energy per bit (EPB). Bandwidth density depends on wiring density, wire length, and signaling data rate on each wire. Signal speed is determined primarily by the dielectric constant. Low wire capacitance can be achieved by shorter wires between dies and low dielectric constant materials. Therefore, there is need for integration of ultra-low k materials in the redistribution wiring layers (RDLs) of the package. Earlier studies involved materials having dielectric constant in the range of 2.65 to 3.2. 

It has been reported that when the dielectric constant (k) is reduced from 3.9 to 2.4, the EPB is reduced by 40%. Therefore, the present study evaluates ultra-low-k dielectric materials which have dielectric constant in the range of 2.1 to 2.4 with respect to different reliability aspects. This study describes electrical characterization of these materials by measuring the insertion losses in the range of 10-170 GHz and losses. Typically, the ultra-low-k materials have inert chemistries and there is a possibility of lower adhesion to metal layers. Therefore, there is a need to study chemical reliability. This study involves improving the adhesion between dielectric and metal layer by optimizing plasma processes and curing condition. The effect of Vapor Phase Infiltration (VPI) on adhesion of these materials has been studied. Another aspect of chemical reliability is moisture absorption. This is evaluated by comparing the behavior of these materials before and after highly accelerated stress test (HAST). For the ultra-low-k materials to be suitable for use in RDL having high wiring density, there is need to demonstrate fine line features and formation of vias. Therefore, fabrication of fine line features has been demonstrated on these materials. The effect of seed layer thickness and surface roughness on the resolution of fine lines and spaces has been studied. Methodologies have been developed to measure via dimensions since reliability of vias depends on their dimension. In addition, different methods to measure the coefficient of thermal expansion (CTE) of these thin polymer dielectric films and VPI has been explored as a method to reduce CTE.