Title:  Design of High-Performance and Energy-Efficient Interconnection Systems for Heterogeneous Multi-Chiplet Graphic Processing Units

Committee: 

Dr. Krishna, Advisor

Dr. Kim, Chair

Dr. Raychowdhury

Dr. Beckmann

Abstract: The objective of the proposed research is to develop architectures, tools, and methodologies for the design of modern multi-chiplet GPU processors and unlock performance and power efficiency gains. The end of Dennard scaling followed by the slowing of Moore's law has made computer systems increasingly complex, with the integration of not just multiple types of processing units but also multiple disintegrated chiplets on a single package. The adoption of multi-chiplet architectures by commercial vendors has propelled the need to develop new designs, tools, and methodologies for building high-performance and energy-efficient next-generation systems. Chiplet-based systems introduce several new design constraints and pose challenging research questions. Unfortunately, current state-of-art architectures and design methodologies do not efficiently adapt to the new constraints posed by these packaging technologies. Additionally, with the dramatic increase in the usage of Graphics Processing Units (GPUs) for general-purpose computation, it has become particularly important to optimize solutions for them. Thus, there is a broad need to revisit the system research and design approaches for these multi-chiplet GPUs. This thesis proposes to address some of these challenges by exploring GPU and interconnection system architectures, developing tools and methodologies, and proposing novel designs to enable efficient and tighter integration on next-generation GPU systems.