Title:  EDA for High-performance and Reliable 3D Memory Cubes and Processors

Committee: 

Dr. Lim, Advisor  

Dr. Yu, Chair

Dr. Krishna

Abstract: The objective of the proposed research is to explore various design methodologies and related architectures for high-performance and reliable 3D designs of memory cubes and processors. First, we develop a new die stacking architecture targeting space applications that leverages the high radiation hardness of commercial DRAM and NAND flash dies. Then, we design custom radiation-hardened-by-design (RHBD) logic controllers that fully exploit the new proposed configurations of our DRAM and NAND flash cubes. We also present a power, performance, area, and cost analysis of large-scale manycore 3D memory-on-logic processors. Finally, in the remaining part of the research, we will propose improvements to a Memory-On-Logic EDA flow towards a more holistic approach as well as develop a PPA-aware tier partitioner enhanced with reinforcement learning algorithms.