Georgia Tech ECE Compute In-Memory Research Team Wins Best Paper Award

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Sidebar Content
No sidebar content submitted.
Summaries

Summary Sentence:

ECE Ph.D. students Brian Crafton, Samuel Spetalnick, and Gauthaman Murali and their faculty advisors won the Best Paper Award at this year's IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020).

Full Summary:

ECE Ph.D. students Brian Crafton, Samuel Spetalnick, and Gauthaman Murali and their faculty advisors won the Best Paper Award at this year's IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020).

Media
  • Georgia Tech ECE Compute In-Memory Research Team Georgia Tech ECE Compute In-Memory Research Team
    (image/png)

Brian Crafton, Samuel Spetalnick, and Gauthaman Murali and their faculty advisors won the Best Paper Award at this year's IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020). The conference was held October 5-7 in a virtual format.

Crafton, Spetalnick, and Murali are all Ph.D. students in the Georgia Tech School of Electrical and Computer Engineering (ECE). Crafton and Spetalnick are advised by ECE Professor Arijit Raychowdhury, and Murali is advised by ECE Professor Sung-Kyu Lim. ECE Assistant Professor Tushar Krishna also joins Raychowdhury, Lim, and their students as co-authors on the paper.

The title of their work is "Breaking Barriers: Maximizing Array Utilization for Compute In-Memory Fabrics." Compute In-Memory using emerging non-volatile memory technologies is an exciting technique that promises to minimize data transport, maximize memory throughput, and perform compute on the bitline of memory sub-arrays, thus accelerating machine learning and neuromorphic applications. However, this technique faces new challenges not faced in traditional CMOS memory fabrics. While the new memories provide high density and near-zero leakage power, they require significantly higher write energy than traditional CMOS-based memories. As a result, it is not practical to write the memories at high rates.

This work presents a novel technique to partition the data to be stored in the memory, by intelligently profiling the application in advance. The team demonstrates that for their target application, different operations in the workload require different time to execute on the same hardware. Using this insight, memory can be fairly allocated to maximize throughput and achieve significant speedup over prior work.

This research is funded by the Air Force Office of Scientific Research through the CEREBRAL MURI program and by SRC through the JUMP programs.

Photo caption (clockwise from upper left): Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Tushar Krishna, Sung Kyu Lim, and Arijit Raychowdhury

 

Related Links

Additional Information

Groups

School of Electrical and Computer Engineering

Categories
Student and Faculty, Student Research, Research, Computer Science/Information Technology and Security, Engineering
Related Core Research Areas
Data Engineering and Science, Electronics and Nanotechnology
Newsroom Topics
No newsroom topics were selected.
Keywords
Brian Crafton, Samuel Spetalnick, Gauthaman Murali, Arijit Raychowdhury, Georgia Tech, School of Electrical and Computer Engineering, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SoC 2020), compute in-memory, computer in-memory fabrics, non-volatile memory technology, data transport, memory throughput, machine learning, neuromorpic applications, CMOS memory fabrics, Air Force Office of Scientific Research, CEREBRAL MURI Program, SRC, JUMP programs
Status
  • Created By: Jackie Nemeth
  • Workflow Status: Published
  • Created On: Nov 3, 2020 - 12:07pm
  • Last Updated: Nov 3, 2020 - 2:55pm