MS Defense by Srinidhi Suresh

Event Details
  • Date/Time:
    • Monday April 13, 2020
      10:00 am - 12:00 pm
  • Location: REMOTE
  • Phone:
  • URL: WebEx
  • Email:
  • Fee(s):
    N/A
  • Extras:
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Summaries

Summary Sentence: "Modeling, Design and Fabrication of Substrate-Embedded Inductors with high inductance density and low DC resistance for Integrated Voltage Regulators

Full Summary: No summary paragraph submitted.

THE SCHOOL OF MATERIALS SCIENCE AND ENGINEERING

 

GEORGIA INSTITUTE OF TECHNOLOGY

 

Under the provisions of the regulations for the degree

MASTER OF SCIENCE

on Thursday, April 16, 2020

1:00 PM
via

WebEx

https://gatech.webex.com/gatech/j.php?MTID=med8f85e42410fb9aa6da08fbdf0f1f3a

 

(Backup location in case of a closed room defense is MaRC 201)

 

will be held the

 

MASTER’S THESIS DEFENSE

for

 

Srinidhi Suresh

 

"Modeling, Design and Fabrication of Substrate-Embedded Inductors with high inductance density and low DC resistance for Integrated Voltage Regulators"

 

Committee Members:

 

Prof. Rao R. Tummala, ECE/MSE

Prof. Madhavan Swaminathan, ECE/MSE

Prof. Hamid Garmestani, MSE

 

Abstract:

 

There is an increasing need for voltage regulators to be integrated closer to active devices such as CPUs and GPUs. These integrated voltage regulators (IVRs) provide numerous performance benefits including higher efficiency, lower parasitics, and increased functionality while miniaturizing the overall system size. However, passive components i.e. inductors, generally occupy the largest volume in power distribution networks (PDNs). Therefore, realizing high-density inductors with ultra-thin form-factors is the main bottleneck to enable highly miniaturized heterogeneous integration of IVRs. An approach that can design cores and topologies with ultra-high inductance density without increasing the real-estate by using low-cost integration processes is required to address the challenges of developing inductors for IVRs.

 

Metal-polymer composites (MPCs)-based interleaved substrate-embedded toroid inductors can meet all the criteria. MPCs as cores for inductor packages have high permeability, high resistivity, low eddy current losses and high frequency stability. An embedded interleaved toroid inductor topology using MPC cores can provide 50% more inductance, 33% higher Q-factor for the same DC resistance compared to an embedded solenoid topology. The combination of better material properties of MPCs, with an efficient toroid topology provides very high inductance densities at smaller inductor sizes, while maintaining low losses and DC resistance. The proposed work aims to improve upon current material approaches for inductor fabrication by providing better density, reduced thickness and DC resistance in a package-integrated format. This work aims to provide a basic understanding of the performance of a single-inductor using embedded toroid approach and the properties that govern its electrical behavior which can be further be scaled to coupled/tapped inductors in next-generation systems.

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Graduate Studies

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Faculty/Staff, Public, Graduate students, Undergraduate students
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Keywords
ms defense
Status
  • Created By: Tatianna Richardson
  • Workflow Status: Published
  • Created On: Mar 19, 2020 - 4:18pm
  • Last Updated: Mar 27, 2020 - 11:13am