PhD Proposal by Bartlet DeProspo

Event Details
  • Date/Time:
    • Tuesday December 3, 2019 - Wednesday December 4, 2019
      1:00 pm - 2:59 pm
  • Location: MaRC 201
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Summary Sentence: Modeling, Design and Demonstration of 1 µm Low Resistance Panel Redistribution Layer Technologies for High Performance Computing Applications

Full Summary: No summary paragraph submitted.





Under the provisions of the regulations for the degree


on Tuesday, December 3, 2019

1:00 PM
in MaRC 201


will be held the





Bartlet DeProspo


"Modeling, Design and Demonstration of 1 µm Low Resistance Panel Redistribution Layer Technologies for High Performance Computing Applications”


Committee Members:


Prof. Rao Tummala, Advisor, ECE/MSE

Prof. Madhavan Swaminathan, ECE/MSE

Prof. Paul Kohl, ChBE

Prof. Azad Naeemi, ECE

Leonel Arana, Ph.D., Intel Corporation




There has been tremendous research in driving the technologies for integrated circuit (IC) device scaling since the mid-1900s. The primary driver of device scaling, Moore’s Law, states that the number of transistors in an integrated circuit (IC) doubles every two years. As IC device scaling is slowing down in recent times, new solutions are being undertaken to improve performance of the entire system. Since 2010, heterogeneous integration of multiple ICs on to a package substrate has become one of the most popular solutions to improve system performance and miniaturization to support high performance computing (HPC) applications. Thus, package substrate technology has been a huge enabler to system scaling in terms of overall miniaturization, high bandwidth performance and high density of interconnections between heterogeneous dies to enable more operations per second.


The research proposed in this thesis work focuses on the redistribution layer (RDL) technology for high density interconnections between two ICs. The state of the art HPC applications utilize silicon back-end-of-line processing for high bandwidth capable of scaling RDL critical dimensions to submicron. However, they face two challenges in terms of: (A) High RC delay RDL wiring connections slowing down the system performance, (B) Limited aspect ratio scaling due to mechanically unstable dielectrics. Glass interposer is a promising alternative solution to this problem. The polymer dielectric based RDL technology for panel platforms is still limited to 5-6 micron features and the proposed research focuses on scaling to 1 micron RDL in three target areas: (A) Modeling and Design for high density and low resistance 1 micron RDL, (B) Fundamental development and performance evaluation of materials for the fabrication of 1 micron RDL on panel platforms and, (C) Innovative process solutions for scaling glass panel RDL to 1 micron line, space and via.


The first target area addresses the modeling and design for high density and high performance 1 micron RDL to understand impact of aspect ratio and design rules for maximization of performance. The second area focuses on developing and evaluation of fundamental differences between materials used in BEOL processing for achieving sub-micron resolutions and those utilized in panel scale process. The goal of this material evaluation and development is to scale the lithographic performance as well as support high aspect ratio traces. The third and final area will focus on the study of substrate impacts on the ability to fabricate high performance 1 micron RDL on panel format technologies. This third area will also focus on innovative processing solutions for scaling seed layer etch as well as via resolution and alignment.

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Graduate Studies

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Faculty/Staff, Public, Graduate students, Undergraduate students
Phd proposal
  • Created By: Tatianna Richardson
  • Workflow Status: Published
  • Created On: Nov 20, 2019 - 12:31pm
  • Last Updated: Nov 20, 2019 - 12:31pm