Title:  Design and Demonstration of SiC 3D Stacked Power Module with Minimized Electrical Parasitics, and Enhanced Thermal and Reliability Performances

Committee: 

Dr. Tummala, Advisor

Dr. Swaminathan, Co-Advisor 

Dr. Saeedifard, Chair

Dr. Joshi

Dr. Smet

Abstract:

The objective of this proposed research is to design and demonstrate a new class of low parasitics, 3D power module for EV/HEV applications with high-efficiency, high dv/dt capability, and enhanced thermal management considering the thermomechanical reliability. Although, recent SiC power devices show excellent electrical performances such as low-conduction loss and high-switching speed, these advantages of new semiconductors are often diminished by conventional package structure which suffer from high parasitic elements. Also, the conventional packaging has limitations handling high heat fluxes that are expected from the SiC devices. This aggravated thermal densities within the package has potential to deteriorate the reliability of the power module. A novel 3D packaging approach will be demonstrated to address the electrical, thermal, and reliability challenges of SiC power modules.