Phd Proposal by Shreya Dwarakanath

Event Details
  • Date/Time:
    • Monday June 17, 2019 - Tuesday June 18, 2019
      11:00 am - 12:59 pm
  • Location: GTMI 431
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Summary Sentence: "Ultra-low K Re-distribution Layer (RDL) Dielectric Materials, Processes and Characterization

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Under the provisions of the regulations for the degree


on Monday, June 17, 2019

11:00 AM
in GTMI 431


will be held the





Shreya Dwarakanath


"Ultra-low K Re-distribution Layer (RDL) Dielectric Materials, Processes and Characterization"

 Committee Members:


Prof. Rao Tummala, Advisor, MSE

Prof. Mark Losego, Co-Advisor, MSE

Prof. Raj Pulugurtha, Florida International University

Prof. C.P. Wong, MSE

Prof. Natalie Stingelin, MSE




The increase in the number of connected devices in homes, cars and offices as well as the need for cloud computing has been driving an unprecedented need for integrating multi-functional chips within a system. The primary goal of a system is to maximum data throughput or bandwidth between the chips. Bandwidth is driven by two factors—number of input-output connections or (I/Os) and the bit rate per I/O. The number of I/Os are determined by the wiring density. Bit rate is determined by signal speed and interconnect length. The need for high bandwidth, is driving the need for maximizing wiring density and high speed connections. While these characteristics have been well established on the chip-side, they are not achieved on the package or system side. Thereby, the trend from a systems perspective is to move towards high-speed high-wiring density interconnections.

(1) Signal speed is determined primarily by the dielectric constant or Dk of the dielectric material. The critical challenge is to develop a polymer material system with optimal physical (ultra-thin), mechanical (low stress) and chemical properties (good adhesion) along with ultra-low Dk. This is the first task of the proposed research, to develop ultra-low Dk Re-Distribution Layer (RDL) materials. (2) Wiring for high I/O density requires multiple layers of RDL wiring at fine line-widths (<2 µm) and line-spaces (<2 µm). The wiring density depends on the thickness of the polymer and process parameters such as surface planarity which enable fine-pitch features. Thus, the second objective of the proposed research includes developing processes for fine-pitch features and good surface smoothness with optimal dielectric height. (3) As the RDL scales to finer pitches, it becomes challenging for the copper lines to adhere to the dielectric. This problem is aggravated by the choice of ultra-low Dk dielectric material which inherently is non-polar and does not have adequate bonding groups. Further, ultra-thin dielectric materials in multi-layer RDL increases the residual stress as the copper percentage in the RDL increases. This can lead to dielectric/copper cracking or delamination. Hence, the third objective of this proposed research is to characterize the residual stress and adhesion of the RDL dielectric/metal layers.

In addressing the barriers stated above, this thesis investigates polymer material systems in their compatibility for RDL in terms of material properties, ease of fabricating fine-pitch features on smooth surfaces and finally, low residual stress and good adhesion. Thus, this thesis focuses on developing RDL dielectric materials, processes and characterization to meet the needs of ultra-high-bandwidth for next-generation of high-performance computing.

Additional Information

In Campus Calendar

Graduate Studies

Invited Audience
Public, Graduate students, Undergraduate students
Phd proposal
  • Created By: Tatianna Richardson
  • Workflow Status: Published
  • Created On: Jun 6, 2019 - 3:51pm
  • Last Updated: Jun 6, 2019 - 3:51pm