Crafton, Chang Tapped for Qualcomm Innovation Fellowship

Contact

Jackie Nemeth

School of Electrical and Computer Engineering

404-894-2906

Sidebar Content
No sidebar content submitted.
Summaries

Summary Sentence:

ECE Ph.D. student Brian Crafton and Muya Chang have won the 2019 Qualcomm Innovation Fellowship, which recognizes and rewards teams of two Ph.D. students each and their thesis advisor(s).

Full Summary:

ECE Ph.D. student Brian Crafton and Muya Chang have won the 2019 Qualcomm Innovation Fellowship, which recognizes and rewards teams of two Ph.D. students each and their thesis advisor(s).

Media
  • Brian Crafton and Muya Chang Brian Crafton and Muya Chang
    (image/jpeg)

Brian Crafton and Muya Chang have won the 2019 Qualcomm Innovation Fellowship, which recognizes and rewards teams of two Ph.D. students each and their thesis advisor(s). Crafton and Chang are both Ph.D. students in the Georgia Tech School of Electrical and Computer Engineering (ECE) and are members of the Integrated Circuits and Systems Research Lab. They are advised by ECE Associate Professor Arijit Raychowdhury. 

The research range for this fellowship is broad and based on Qualcomm’s core business and research areas. The winners are judged through a rigorous process that includes submission of a research abstract, a research proposal, and a presentation and a poster session. This year, the fellowship has been awarded to 13 teams from a total of 115 submissions from 22 schools. 

Crafton's and Chang’s proposal is entitled “Enabling Efficient Training of Deep Neural Networks through Sparse Direct Feedback Alignment and Algorithm-Hardware Co-Design.” This proposes a bio-plausible alternative to back-propagation of errors for real-time learning in neural networks. Here the error computation at a single synapse is local and avoids the weight propagation problem. 

Based partly on Crafton’s prior work on sparse feedback alignment and Chang’s work on near-memory computing architectures and IC design, the team demonstrated the possibility of reducing data-movement by orders of magnitude for classification and regression problems. This enables local learning rules based on a single error propagation, fast and parallel updates of all synapses in the network, and high energy-efficiency when realized in hardware.

Related Links

Additional Information

Groups

School of Electrical and Computer Engineering

Categories
Student and Faculty, Student Research, Research, Computer Science/Information Technology and Security, Engineering, Nanotechnology and Nanoscience, Physics and Physical Sciences
Related Core Research Areas
Data Engineering and Science, Electronics and Nanotechnology
Newsroom Topics
No newsroom topics were selected.
Keywords
Brian Crafton, Muya Chang, graduate students, Georgia Tech, School of Electrical and Computer Engineering, Integrated Circuits and Systems Research Lab, Arijit Raychowdhury, qualcomm, Qualcomm Innovation Fellowship, neural networks, sparse direct feedback alignment, algorithm-hardware co-design, near-memory computing architectures, IC design, data-movement, classification problems, regression problems, local learning rules, single error propagation, high-energy efficiency, hardware
Status
  • Created By: Jackie Nemeth
  • Workflow Status: Published
  • Created On: Jun 4, 2019 - 10:31am
  • Last Updated: Jun 5, 2019 - 11:44am