Title:  Experimental Benchmarking of CVD Graphene for Memory and Interconnect Applications

Committee:

Dr. Azad Naeemi, ECE, Chair , Advisor

Dr. Muhannad Bakir, ECE

Dr. Eric Vogel, MSE

Dr. Jeffrey Davis, ECE

Dr. Francky Catthoor, Katholieke Universiteit Leuven

Abstract:

The continuous increase in the 3D memory density required an increase in the height of the 3D stack. This, in turn, dictated an increase in the width of the memory hole which is accompanied by a reduction in the electric field inside the memory hole. To compensate for the reduced electric field, an increase in the programming voltage and/or programming time is required at the expense of higher power dissipation and/or slower memory operation. Furthermore, with the continuous scaling of feature size, interconnects become the dominating factor in determining the performance of electronic circuits due to increased RC delay of interconnects, increased crosstalk between nearby interconnect lines, increased dynamic power dissipation, and reliability issues due to electron migration. In this thesis, we study CVD-grown graphene as a potential candidate for memory as well as electrical interconnects applications. Graphene can compensate for the reduced electric field in 3D memory devices while keeping the programming voltage sufficiently low by enhancing the electric field at its atomically-thin, sharp edges. Furthermore, Graphene is considered a promising alternative to copper interconnects owing to its current carrying capability that can reach 108 A/cm2, ultrahigh intrinsic carrier mobility, and low resistivity.