Variation-aware and Process-sensitive Reliabilty Stimulator and its Applications for Analog and Digital Circuits

Committee:

Dr. Linda Milor, ECE, Chair , Advisor

Dr. Azad Naeemi, ECE

Dr. Abhijit Chatterjee, ECE

Dr. Shimeng Yu, ECE

Dr. Hao-Min Zhou, Math

Abstract:

The objective of this research is to investigate the impact of traditional gate oxide time dependent dielectric breakdown (TDDB) and the newly emerged middle-of-line (MOL) TDDB in both digital and analog circuits’ reliability. First, we propose a methodology and its corresponding algorithms to extract vulnerable features for gate oxide time dependent dielectric breakdown and middle-of-line (MOL) TDDB for both CMOS and FinFET technology. Combined with vulnerable features, a circuits’ activity profile and temperature map are used for the lifetime calculation of the circuit. Second, we incorporate process variation into our lifetime simulator and analyze its impact on circuit lifetime by using Monte Carlo simulation. Third, with the simulator built, we can find the optimal test region for both mechanisms and optimize the circuit based on performance, area and lifetime trade-off.