Title:  Physical Design Solutions for 3D ICs and their Neuromorphic Applications

Committee: 

Dr. Lim, Advisor 

Dr. Mukhopadhyay, Chair

Dr. Raychowdhury

Abstract:

The objective of this proposed research spans from addressing the power integrity issue of transistor-level M3D ICs to design and CAD methodologies for high-quality gate-level F2F and M3D ICs and their neuromorphic applications. In the completed part of this research, we first present a optimized transistor-level M3D standard cell layout scheme named stitching scheme, and show that our layout optimization improves the full-chip power integrity as well as power-performance-area savings of transistor-level M3D ICs. Next, we study the cost and inter-tier variation impacts on gate-level M3D ICs to justify the adoption of M3D integration in the advanced technology nodes. Then, we present the unique physical design solution named Compact-2D flow, which produces commercial-quality gate-level F2F and M3D ICs layouts. Compact-2D flow does not require geometric scaling. Instead, it scales the 2D interconnect parasitics to mimic the parasitics of 3D routing. Also, Compact-2D supports post-tier-partitioning optimization, and builds timing-robust gate-level 3D ICs. Finally, we adopt the liquid state machine architecture to build an online machine-learning hardware platform, and study the power-performance-area benefits of F2F and M3D ICs on the non-trivial speech recognition applications. For the remaining part of this research, we will apply our 3D design methodologies to the mixed-signal memristive neuromorphic processor design, which will offer an energy-efficient, in-parallel, high-performance non-Von Neumann hardware machine learning platform. Also, we will improve our physical design solutions by applying various machine learning algorithms to enhance the runtime and the layout quality of 3D ICs.