Title:  A Holistic Study of Interconnect Technology: from Modeling Theory to Physical Design of Modern Semiconductor ICs

Committee:

Dr. Azad Naeemi, ECE, Chair , Advisor

Dr. Jeffrey Davis, ECE

Dr. Muhannad Bakir, ECE

Dr. Saurabh Sinha, ARM Research

Dr. Francky Cathoor, Katholieke Universiteit Leuven

Abstract:

The objective of this research is to present a holistic study of the on-chip Copper interconnect technology, from interconnect modeling to their manifestation in modern design implementations in the advanced technology landscape. With the onset of critical size-effects of Copper wires in rigorously scaled technology, interconnect analysis and optimization is of utmost importance. Advanced Cu/low­­-k interconnects are evaluated in physical designs that are based on high-performance FinFET transistors. It is found that the high-capacitance FinFET transistors amplify the impact of interconnect resistance on circuit timing. Furthermore, interconnect resistance variability, due to systematic variability sources in manufacturing, is found to severely limit circuit performance and yield. Therefore, an alternate interconnect sizing regime is proposed that alleviates wire resistance at the cost of wire resistance to better cater to the high-performance designs. This approach is targeted to optimize performance and power, and in the best case, found to improve the performance by 2x and reduce the impact of interconnect variability. Additionally, an alternate patterning technology is proposed to further reduce the impact of interconnect variability on circuit performance and power. While these optimizations target high-performance applications, contrasting implications on interconnect design are observed for low-power designs based on Tunnel-FET (TFET) technology. Low-power devices, like TFET, exhibit low-capacitance and high channel resistance; therefore reduce the impact of interconnect resistance on circuit performance and power. This is validated on full timing-closed layouts, and an optimal interconnect design is proposed to improve the performance and power of low-power circuits. As we approach the end of the technology roadmap, reliable system-level models with accurate interconnect representation are pivotal to early benchmarking and pathfinding efforts. A popular modeling regime, based on Rent’s rule, is modernized and validated in the advanced technology landscape. The proposed models accurately capture the interconnect characteristics of design, and are calibrated to data from state-of-the-art commercial designs. Furthermore, novel critical-path models are proposed to capture trends in technology and microarchitecture facilitating a reliable foundation for technology and design pathfinding.