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Nano@Tech with John Knickerbocker

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Nano@Tech welcomes Dr. John Knickerbocker, IBM Distinguished Engineer and Master Inventor, on "3D Technology for Systems Applications" as part of its weekly seminar series.

Lunch is available for those who pre-register by Friday, August 20.

Abstract:
Three-dimensional (3D) chip integration can provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage high bandwidth electrical and optical interconnection using  stacked die, silicon packages and / or opto-electronics depending on applications.  3D enabling technology elements include: (i) through-silicon-vias (TSV) in thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between die, (iv) known-good die including BIST, fine pitch probes and test strategy and (v) power delivery and cooling solutions.  Applications may range from miniaturization for portable electronics like image sensors and cell phones to high performance computing solutions such as servers and super computers.

About Nano@Tech:
Nano@Tech is an organization comprised of professors, graduate students, and undergraduate students from the Georgia Tech and Emory campuses and professionals from the corresponding scientific community that are interested in Nanotechnology. Meetings are held on the second and fourth Tuesday of each month during the academic year at noon in the Marcus Nanotechnology Building 

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Status

  • Workflow Status:Published
  • Created By:Michael Hagearty
  • Created:08/17/2010
  • Modified By:Fletcher Moore
  • Modified:10/07/2016