Title:  On-die Adaptive Power Regulation and Distribution for Digital Loads

Committee: 

Dr. Raychowdhury, Advisor  

Dr. Yalamanchili, Chair

Dr. Wang

Abstract:

The objective of this work is to provide a power architecture solution where guardband reduction and consistent performance are the key-goals for power delivery network in multicore SoCs.  The necessity for maximizing energy efficiency without compromising performance has led to the implementation of fine-grain Dynamic Voltage and Frequency Scaling (DVFS). However, as DVFS schemes support ever increasing supply-frequency operating points, static and dynamic variations result in increasing design guard-bands and impact the system power efficiency.  The proposed research will attempt to address these concerns through multiple approaches geared towards the different components in the power delivery network hierarchy. Digital assists for analog LDOs, novel approach of integrating clocking and supply voltage loops and elastic and multiple output switched capacitor networks, including theoretical models and measurements from silicon test-chips, will be discussed. As a part of the proposed research, design, analysis and verification of different techniques will be performed through test-chips built in scaled CMOS processes.