Abstract:

Good engineering practice uses the characteristics of existing technologies to optimize implementation. However, this means that design techniques used in a previous generation often prove to be impractical or even unusable when a new technology becomes dominant. This rule is all too often forgotten, which we will demonstrate in two problems of computer design: Field-Programmable Gate Arrays (FPGA) and hardware prefetchers (providing the ability to fetch data early in anticipation of the need). FPGAs are extremely useful in mobile embedded systems where computing power and energy considerations are major concerns. Partial reconfiguration is often used to reduce power consumption when parts of the array are inactive, albeit at the cost of high energy overhead due to the large cost of transferring configuration information. Our study reveals that partial reconfiguration accelerates execution and reduces overall energy consumption by half. Second, we will demonstrate how increased transistor integration allows hardware prefetching to improve both energy-efficiency and performance.

Bio:

Jean-Luc Gaudiot received his bachelor's in engineering from ESIEE, Paris, France, and his master's and Ph.D. degrees in computer science from the University of California, Los Angeles.   He is currently a professor in the Electrical Engineering and Computer Science Department at the University of California, Irvine (UCI). Prior to joining UCI in 2002, he was a professor of Electrical Engineering at the University of Southern California. Gaudiot's research interests include multithreaded architectures, fault-tolerant multiprocessors, and implementation of reconfigurable architectures. He has published more than 250 journal and conference papers, and his research has been sponsored by NSF, DoE, and DARPA, as well as private sector companies. He has served the community in various positions and was just elected to the presidency of the IEEE Computer Society for 2017. He is a Fellow of the IEEE and a Fellow of the AAAS.