Title:  NeuroCube: A Programmable Digital Neuromorphic Architecture with High-density 3D Memory

Committee: 

Dr. Mukhopahdyay, Advisor 

Dr. Yalamanchili, Chair

Dr. Kim

Abstract: The objective of the proposed research is design neuromorphic architecture, which should be energy efficient, scalable, and programmable. For high energy efficiency, limited memory bandwidth, which is the bottleneck of entire system, should be solved. To solve this problem, I proposed neuromorphic architecture as processor-in-memory within 3D stacked DRAM system. Scalable neuromorphic architecture means that given hardware should cover various size of neural network without hardware modification. For deep neural network, especially fully connected one, storing all states and synaptic weights in on-chip cache memory is impractical. In this paper, I suggest storing all states and synaptic weights are stored in 3D stacked high density memory. Therefore, the maximum size of network is limited by DRAM capacity, which is quiet large enough. This approach differs from designing hardware module for each neuron and implementing synaptic connections using hard wire (routing) or rely on on-chip cache memory. Since optimal neural network structure is debatable research topic, fixed hardware for specific neural network is not practical. Like GPGPU or CPU, proposed architecture is programmable to cover different types of neural networks. Most of prior digital neuromorphic accelerator focused on specific neural network, mostly convolutional neural network. Based on the proposed architecture, it will be implemented on field programmable gate array (FPGA) and tested with real-time application.