Title:  Desgin and Test Methodologies with Statistical Analysis for Reliable Memory and Processor Implementations

Committee:

Dr. Milor , Advisor

Dr. Abhijit Chatterjee, ECE

Dr. Azad Naeemi, ECE

Dr. David Schimmel, ECE

Dr. Haomin Zhou, Math

Abstract: 

The object of the proposed research is to develop methodologies to diagnose wearout in an SRAM array and to monitor the system health using the diagnosis results. The proposed research has presented built-in self-test system and statistical analysis methodologies for electrical detection and diagnosis of wearout mechanisms in an SRAM. We also propose to use the embedded SRAM as a monitor of system health. The bit failures are tracked with error correcting code (ECC) and the cause of each bit failure is diagnosed with on chip built-in self test (BIST) system. The wearout model parameters are estimated from the diagnosis results and combined with system wearout simulator to estimate the remaining lifetime of the entire processor. This work has been proposed with a variety of approaches, including electrical system design, statistical analysis, and developing new simulation workflows.