PhD Defense by Brian Railing

Event Details
  • Date/Time:
    • Friday October 30, 2015
      3:00 pm - 5:00 pm
  • Location: MiRC 102B
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Summary Sentence: Collecting and Representing Parallel Programs with High Performance Instrumentation

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Title: Collecting and Representing Parallel Programs with High Performance Instrumentation

 

Brian Railing

School of Computer Science
College of Computing
Georgia Institute of Technology

Date: Friday, October 30, 2015
Time: 3:00 PM – 5:00 PM ET
Location: MiRC 102B

 

Committee:

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Dr. Thomas Conte (Advisor, School of Computer Science and School of Electrical and Computer Engineering, Georgia Tech)

Dr. Santosh Pande (School of Computer Science, Georgia Tech)

Dr. Richard Vuduc (School of Computational Science and Engineering, Georgia Tech)

Dr. Sudhakar Yalamanchili (School of Electrical and Computer Engineering, Georgia Tech)

Dr. Bruce Worthington (Partner Computer Engineering Lead, Microsoft)

 

Abstract:

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Computer architecture has looming challenges with finding program parallelism, process technology limits, and limited power budget.  To navigate these challenges, a deeper understanding of parallel programs is required. I will discuss the task graph representation and how it enables programmers and compiler optimizations to understand and exploit dynamic aspects of the program.

 

I will present Contech: a high performance framework for generating dynamic task graphs from arbitrary parallel programs.  The Contech framework supports a variety of languages and parallelization libraries, and has been tested on both x86 and ARM.  I will demonstrate how this framework encompasses a diversity of program analyses, particularly by modeling a dynamically reconfigurable, heterogeneous multi-core processor.

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Phd Defense
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  • Created By: Tatianna Richardson
  • Workflow Status: Published
  • Created On: Oct 14, 2015 - 10:58am
  • Last Updated: Oct 7, 2016 - 10:14pm