Speaker: Ram Krishnamurty, Intel Labs, Hillsboro, Ore.

Title: "High-Performance and Low-Voltage DSP Accelerator Circuits for Tera-Scale Multi-Core Microprocessors and SoCs"

Abstract

With the emergence of high-performance multi-core microprocessors and ultra-low-power systems-on-chip in the sub-22nm technology era, specialized hardware accelerator engines embedded within the core architecture have the potential to achieve 10-100X increase in energy efficiency across a wide domain of compute-intensive signal processing and scientific algorithms. In this talk, we present multi-core microprocessors and SoCs integrated with on-die energy-efficient reconfigurable accelerator and co-processor engines to achieve well beyond tera-scale performance in sub-22nm technologies. Recent trends and advances in multi-core microprocessors will be presented, followed by key enablers for reconfigurability of specialized hardware engines to support multiple protocols while substantially improving time-to-market and amortizing die area cost across a wide range of compute workloads and functions. Specific design examples and case studies supported by silicon measurements will be presented to demonstrate reconfigurable engines for signal processing and graphics/media applications. Power efficient optimization of processors to support fine-grain power management, integrated voltage regulators, resilient circuit design, dynamic on-the fly configurability and circuit techniques for standby-mode leakage reduction and low-voltage operability will be described.

Speaker Biography

Ram K. Krishnamurthy is a senior principal engineer with Circuits and Systems Research, Intel Labs in Hillsboro, Ore., where he heads the high-performance and low-voltage circuits research group. He received the B.E. degree in Electrical Engineering from Regional Engineering College, Trichy, India, in 1993, and the Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, PA, in 1998. He has been with Intel Corporation since 1998.

Dr. Krishnamurthy holds 95 issued patents and has published over 125 conference/journal papers and 3 book chapters on high-performance energy-efficient microprocessor design. He serves as Intel's representative on the SRC Integrated Circuits and Systems Sciences Task Force, has been a guest editor of the IEEE Journal of Solid-State Circuits and on the technical program committees of the ISSCC, CICC, and SOCC conferences. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference and presently serves on the conference's steering committee.

Dr. Krishnamurthy has served as an adjunct faculty of the Electrical and Computer Engineering department at Oregon State University, where he taught advanced VLSI design. He has received the IEEE International Solid State Circuits Conference Distinguished Technical Paper Award in 2012, the European Solid State Circuits Conference Best Paper Award in 2012, Outstanding Industry Mentor Award from SRC in 2002 and 2011, Intel Awards for most patents filed in 2001 and most patents issued in 2003, Alumni recognition award from Carnegie Mellon University in 2009, and the MIT Technology Review's TR35 Innovator Award in 2006. He has received two Intel Achievement Awards, in 2004 and 2008, for the development and technology transfer of novel high-performance execution core arithmetic circuits and special-purpose hardware encryption accelerators. His research interests are in high-performance/low-power data-path, DSP and on-chip interconnect circuits. He is a Fellow of the IEEE.