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Ph.D. Defense of Dissertation: Minjang Kim

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Ph.D. Defense of Dissertation Announcement
 
Title: Dynamic Program Analysis Algorithms to Assist Parallelization
 
Minjang Kim
Ph.D. candidate in Computer Science
School of Computer Science
College of Computing
Georgia Institute of Technology
minjang@gatech.edu
 
Date: Monday, July 30, 2012
Time: 9:00 am - 11:30 am (EDT)
Location: KACB 2100

 
Committee:

  • Dr. Hyesoon Kim (Advisor, School of Computer Science, Georgia Tech)
  • Dr. Hsien-Hsin S. Lee (School of Electrical and Computer Engineering, Georgia Tech)
  • Dr. Santosh Pande (School of Computer Science, Georgia Tech)
  • Dr. Richard Vuduc (School of Computational Science and Engineering, Georgia Tech)
  • Dr. Chi-Keung (CK) Luk (Intel Corporation)



Abstract:
All market-leading processor vendors have started to pursue multicore processors as an alternative to high-frequency single-core processors for better energy and power efficiency. This transition to multicore processors no longer provides the free performance gain enabled by increased clock frequency for programmers. Parallelization of existing serial programs has become the most powerful approach to improving application performance. Not surprisingly, parallel programming is still extremely difficult for many programmers mainly because thinking in parallel is simply beyond the human perception. However, we believe that software tools based on advanced analyses can significantly reduce this parallelization burden.

Much active research and many tools exist for already parallelized programs such as finding concurrency bugs. Instead we focus on program analysis algorithms that assist the actual parallelization steps: (1) finding parallelization candidates, (2) understanding the parallelizability and profits of the candidates, and (3) writing parallel code. A few commercial tools are introduced for these steps. A number of researchers have proposed various methodologies and techniques to assist parallelization. However, many weaknesses and limitations still exist.

In order to assist the parallelization steps more effectively and efficiently, this dissertation proposes Prospector, which consists of several new and enhanced program analysis algorithms.

First, an efficient loop profiling algorithm is implemented. Frequently executed loop can be candidates for profitable parallelization targets. The detailed execution profiling for loops provides a guide for selecting initial parallelization targets.

Second, an efficient and rich data-dependence profiling algorithm is presented. Data dependence is the most essential factor that determines parallelizability. Prospector exploits dynamic data-dependence profiling, which is an alternative and complementary approach to traditional static-only analyses. However, even state-of-the-art dynamic dependence analysis algorithms can only successfully profile a program with a small memory footprint. Prospector introduces an efficient data-dependence profiling algorithm to support large programs and inputs as well as provides highly detailed profiling information.

Third, a new speedup prediction algorithm is proposed. Although the loop profiling can give a qualitative    estimate of the expected profit, obtaining accurate speedup estimates needs more sophisticated analysis. Prospector introduces a new dynamic emulation method to predict parallel speedups from annotated serial code. Prospector also provides a memory performance model to predict speedup saturation due to increased memory traffic. Compared to the latest related work, Prospector significantly improves both prediction accuracy and coverage.

Finally, Prospector provides algorithms that extract hidden parallelism and advice on writing parallel code. We present a number of case studies how Prospector assists manual parallelization in particular cases including privatization, reduction, and pipelining.

Status

  • Workflow Status:Published
  • Created By:Jupiter
  • Created:07/20/2012
  • Modified By:Fletcher Moore
  • Modified:10/07/2016

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