{"693786":{"#nid":"693786","#data":{"type":"event","title":"Ph.D. Dissertation Defense - Stefan Abi-Karam","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003ETitle\u003C\/strong\u003E\u003Cem\u003E:\u0026nbsp; Machine Intelligence and Datasets for High-Level Hardware Design\u003C\/em\u003E\u003C\/p\u003E\u003Cp\u003E\u003Cstrong\u003ECommittee:\u003C\/strong\u003E\u003C\/p\u003E\u003Cp\u003EDr.\u0026nbsp;Callie Hao, ECE, Chair, Advisor\u003C\/p\u003E\u003Cp\u003EDr.\u0026nbsp;Tushar Krishna, ECE\u003C\/p\u003E\u003Cp\u003EDr.\u0026nbsp;Lee Lerner, ECE\u003C\/p\u003E\u003Cp\u003EDr.\u0026nbsp;Hyesoon Kim, CoC\u003C\/p\u003E\u003Cp\u003EDr.\u0026nbsp;Lizzy John, UT Austin\u003C\/p\u003E","summary":"","format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003EDomain-specific hardware accelerators on FPGAs and ASICs are a primary way to meet the performance and energy demands of applications in science and machine learning, and high-level synthesis (HLS) makes them more accessible by compiling high-level code into hardware. However, producing an optimized HLS accelerator is far harder than producing a working one, and HLS tools leave this expertise to the designer. This dissertation uses emerging machine intelligence to close that gap through three challenges. First, to automate building accelerators, it presents GNNBuilder, which generates HLS accelerators for a broad class of graph neural networks, and FIFOAdvisor, which sizes the FIFO buffers of HLS dataflow designs to reduce memory with minimal latency impact. Second, to build the datasets that data-driven methods require, it presents HLSFactory for standardized dataset construction, SyntheticHLS for generating diverse synthetic designs with large language models (LLMs), and HLSFactory-Agent for extracting designs from open-source and academic repositories. Third, to integrate AI into HLS workflows, it presents HLS-Eval, a benchmark for LLMs on HLS design tasks, and an agent framework that jointly optimizes parameterized designs and their design spaces to produce Pareto-optimal accelerators.\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"Machine Intelligence and Datasets for High-Level Hardware Design "}],"uid":"28475","created_gmt":"2026-11-04 21:32:15","changed_gmt":"2026-11-04 21:32:49","author":"Daniela Staiculescu","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2026-11-11T12:00:00-05:00","event_time_end":"2026-11-11T14:00:00-05:00","event_time_end_last":"2026-11-11T14:00:00-05:00","gmt_time_start":"2026-11-11 17:00:00","gmt_time_end":"2026-11-11 19:00:00","gmt_time_end_last":"2026-11-11 19:00:00","rrule":null,"timezone":"America\/New_York"},"location":"Room 4222, Prince Gilbert","extras":[],"related_links":[{"url":"https:\/\/gatech.zoom.us\/j\/98630851299","title":"Zoom link"}],"groups":[{"id":"434381","name":"ECE Ph.D. Dissertation Defenses"}],"categories":[],"keywords":[{"id":"100811","name":"Phd Defense"},{"id":"1808","name":"graduate students"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1788","name":"Other\/Miscellaneous"}],"invited_audience":[{"id":"78771","name":"Public"}],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}