{"691079":{"#nid":"691079","#data":{"type":"news","title":"Professor Receives Third Test of Time Honor in Three Years","body":[{"value":"\u003Cp\u003EProfessor \u003Ca href=\u0022https:\/\/moin.cc.gatech.edu\u0022\u003EMoinuddin Qureshi\u003C\/a\u003E received the ACM SIGARCH\/IEEE-CS TCCA Influential ISCA Paper Award at the \u003Ca href=\u0022https:\/\/iscaconf.org\/isca2026\/\u0022\u003EInternational Symposium on Computer Architecture\u003C\/a\u003E (ISCA 2026) on June 30.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EPresented annually, the ISCA Influential Paper Award recognizes a standout paper from the ISCA Conference 18-22 years prior. Winning papers are those which have demonstrated \u201cthe most impact on the field (in terms of research, development, products or ideas) during the intervening years.\u201d\u003C\/p\u003E\u003Cp\u003EThe awarded paper, \u003Cem\u003EAdaptive Insertion Policies for High-Performance Caching\u003C\/em\u003E, has been highly influential in cache replacement research. As a Ph.D. student at the University of Texas at Austin, Qureshi co-authored the paper with his advisor Yale Patt and collaborators from Intel, including Aamer Jaleel, Simon Steely, and Joel Emer.\u003C\/p\u003E\u003Cp\u003E\u201cI\u2019ve been working on memory systems for 20 years and if I had to pick one favorite paper, it would be this one,\u201d Qureshi said. \u201cBoth because of the simplicity of the solution and for the impact it had.\u201d\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EWhen the paper was published at ISCA 2007, on-chip cache sizes were growing but still managed almost exclusively by the\u0026nbsp;Least Recently Used (LRU) replacement policy.\u0026nbsp;\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EThe paper showed that more than half of the lines in cache were discarded before they could be used under LRU policy and that this happened because the workloads being run were larger than the cache size. The team came up with a simple solution of modifying the \u201cInsertion Policy\u201d, such that the incoming lines were inserted at the LRU position instead of the MRU position, thus protecting the cache from thrashing patterns. The problem was that some workloads benefited from this policy while others were hurt by it.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EInstead of applying one policy across the whole cache, their solution dynamically tested two small segments against each other, each running a different policy. Whichever policy had fewer cache misses was applied to the entire cache. They named this technique Set Dueling.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EQureshi clearly remembers the moment he knew this paper would be important. He was up late working on the project when he ran the final simulation with the solution.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E\u201cI was so excited that I just didn\u2019t sleep that night. I knew that the solution would get incorporated and it would change how people think about caching. I could not wait to share the results with my collaborators\u201d he said.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003ESet Dueling has since become a common technique for choosing between two competing policies when neither wins on all workloads. With close to 1,000 citations, the paper has greatly influenced research on cache optimization.\u003C\/p\u003E\u003Cp\u003EThis recognition is Qureshi\u2019s third test-of-time honor. In 2024, he received one at the IEEE\/ACM International Symposium on Microarchitecture, for his work on Multi-core Cache Partitioning and in 2025, at the IEEE\/IFIP International Conference on Dependable Systems and Networks, for his work on DRAM Reliability.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003EQureshi said that his goal in working in computer architecture is to have an industry impact.\u0026nbsp;\u003C\/p\u003E\u003Cp\u003E\u201cIt\u2019s very gratifying to see that the ideas that we developed a decade or two decades ago are having an impact and being incorporated,\u201d Qureshi said. \u201cAs a researcher, these are the best awards you can have because it serves as a validation that the work you\u2019ve done is valuable to both industry and follow-up research.\u201d\u0026nbsp;\u0026nbsp;\u003C\/p\u003E","summary":"","format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003EProfessor \u003Ca href=\u0022https:\/\/moin.cc.gatech.edu\u0022\u003EMoinuddin Qureshi\u003C\/a\u003E received the ACM SIGARCH\/IEEE-CS TCCA Influential ISCA Paper Award at the \u003Ca href=\u0022https:\/\/iscaconf.org\/isca2026\/\u0022\u003EInternational Symposium on Computer Architecture\u003C\/a\u003E (ISCA 2026) on June 30. The awarded paper, \u003Cem\u003EAdaptive Insertion Policies for High-Performance Caching\u003C\/em\u003E, has been highly influential in cache replacement research.\u0026nbsp;\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"Professor Moinuddin Qureshi received the ACM SIGARCH\/IEEE-CS TCCA Influential ISCA Paper Award at the International Symposium on Computer Architecture (ISCA 2026) on June 30. "}],"uid":"36532","created_gmt":"2026-07-10 14:44:32","changed_gmt":"2026-07-10 16:36:12","author":"Morgan Usry","boilerplate_text":"","field_publication":"","field_article_url":"","location":"Atlanta, GA","dateline":{"date":"2026-07-10T00:00:00-04:00","iso_date":"2026-07-10T00:00:00-04:00","tz":"America\/New_York"},"extras":[],"hg_media":{"680590":{"id":"680590","type":"image","title":"moin_isca.jpg","body":null,"created":"1783701216","gmt_created":"2026-07-10 16:33:36","changed":"1783701216","gmt_changed":"2026-07-10 16:33:36","alt":"moin","file":{"fid":"264869","name":"moin_isca.jpg","image_path":"\/sites\/default\/files\/2026\/07\/10\/moin_isca.jpg","image_full_path":"http:\/\/hg.gatech.edu\/\/sites\/default\/files\/2026\/07\/10\/moin_isca.jpg","mime":"image\/jpeg","size":163890,"path_740":"http:\/\/hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/2026\/07\/10\/moin_isca.jpg?itok=hFw3xbfW"}}},"media_ids":["680590"],"groups":[{"id":"47223","name":"College of Computing"}],"categories":[{"id":"153","name":"Computer Science\/Information Technology and Security"},{"id":"135","name":"Research"}],"keywords":[{"id":"182764","name":"microarchitecture"},{"id":"175184","name":"computer architecture"},{"id":"170453","name":"Test of Time Award"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cp\u003EMorgan Usry, Communications Officer, morgan.usry@cc.gatech.edu\u003C\/p\u003E","format":"limited_html"}],"email":["morgan.usry@cc.gatech.edu"],"slides":[],"orientation":[],"userdata":""}}}