Rafael Oliveira  

Ph.D. Candidate in Computer Science  

School of Computer Science  

College of Computing  

Georgia Institute of Technology  

Date: Mon, May  18th, 2026

Time:  1:00 PM - 3:00 PM EDT

Location:  TEAMS

Committee:  

Dr. Ada Gavrilovska  (advisor) – College of Computing, Georgia Institute of Technology  

Dr. Calton Pu – College of Computing, Georgia Institute of Technology  

Dr. Santosh Pande – College of Computing, Georgia Institute of Technology  

Dr. Alex Daglis – College of Computing, Georgia Institute of Technology  

Dr. Hadi Esmaeilzadeh – Computer Science and Engineering, University of California San Diego (UCSD)  

Abstract: 

Modern cloud infrastructure faces a fundamental inefficiency: while modern software scales through shared resources—from dynamically linked libraries to containerized microservices—SmartNICs allocate dedicated hardware-accelerator resources per tenant, evoking the pre-DLL era where common functions were duplicated in every program. This wastes precious hardware resources in multi-tenant environments where applications often need the same computations (AES encryption, Kalman filters) with different parameters. This is particularly problematic for streaming-data applications, where large numbers of concurrent sources—organized into topic hierarchies—run identical processing chains that differ only in their per-source parameters.

This thesis introduces parametric Compute Unit (CU) sharing—enabling multiple tenants to share hardware accelerators just as software shares libraries. The key challenges are twofold: managing parameters at line rate, without trading off the benefits that SmartNIC offload provides; and doing so without undue burden on programmers, without major disruption to established programming frameworks.

We present two systems that together address these challenges. Vazado addresses parameter delivery at line rate: through hardware-compiler co-design, it dynamically chains CUs with incompatible signatures, extending CU sharing to parametric tasks that prior dedicated-pipeline systems cannot share—while matching the >100 Gbps throughput of systems like PANIC on just 10% of FPGA resources. ErdTree addresses programmer burden: a domain-aware compiler that automatically translates familiar high-level streaming programs into a correct, efficient implementation of the CU chain and its parameter layout across the accelerator's memory hierarchy—retaining throughput comparable to hand-optimized fixed-parameter offloads while reducing memory footprint by 52% and supporting GB-scale off-chip state.

Together, these systems demonstrate that efficient multi-tenant acceleration is achievable without sacrificing programmability—enabling SmartNICs to finally deliver on their promise of scalable, shared acceleration for cloud infrastructure.