Date: Tuesday, May 5th, 2026

Time: 1:00 - 3:00 PM ET

Location: Klaus 3126

Zoom: https://gatech.zoom.us/j/98919205550

Pulkit Gupta

Ph.D. Student

School of Computer Science
College of Computing
Georgia Institute of Technology

Committee:

Dr. Thomas M. Conte (Advisor) – School of Computer Science, Georgia Institute of Technology

Dr. Hyesoon Kim – School of Computer Science, Georgia Institute of Technology

Dr. Vivek Sarkar – School of Computer Science, Georgia Institute of Technology

Dr. Divya Mahajan – School of Computer Science, Georgia Institute of Technology

Dr. Peter Kogge – College of Engineering, University of Notre Dame

Abstract:

Superconducting digital logic families offer immense energy and power savings over conventional CMOS based electronics. However, superconducting circuits pose significant challenges to designing an architecture with high performance. This thesis proposes 2 architectures, SYNDRA and STRIDE, which attempt to provide high single threaded performance and high system level throughput respectively. SYNDRA (Static Synchronous Dataflow RISC Architecture) overcomes the challenges in conventional high-ILP architectures by offloading all scheduling efforts to a compiler through the Statically Assigned DataGraph Execution (SADGE) model, showing a peak IPC of 4 at 1GHz. STRIDE tackles the latencies of superconducting systems, by proposing a manythreaded system with 512 threads, a per-thread IPC of 0.08, but a system-level IPC of 4 at 5GHz. Together these architectures comprise a Superconducting Unit of Performance (SUP), which allows for both high single-threaded and high system-level throughput. Many SUPs can be composed through the use of a superconducting interconnect to enable supercomputer-scale systems with immense energy efficiency.