689464 event 1775255063 1775255141 <![CDATA[Ph.D. Dissertation Defense - Janak Sharda]]> Title:  Electrical-thermal Co-design and System-level Analysis of Advanced Packaging Solutions for Hardware Accelerators and Sensor Technologies

Committee:

Dr. Shimeng Yu, ECE, Chair, Advisor

Dr. Muhannad Bakir, ECE

Dr. Saibal Mukhopadhyay, ECE

Dr. Tushar Krishna, ECE

Dr. Yingyang (Celine) Lin, CoC

]]> Deep learning solutions are becoming increasingly important for a lot of tasks. Tasks such as object detection from image rely on additional sensors and tasks such as natural language processing performed using large language models (LLMs) require efficient access to large memory capacity. As a result, they require close interconnection between different components for efficient data and signal movement. Heterogeneous integration has been proposed recently to address such concerns. This dissertation proposes designs for various problems ranging from sensing-based edge technologies to large server-based hardware accelerators for LLMs. The work proposes designs and analysis different packaging schemes depending upon the requirements. It proposes heterogeneous integration of different components including emerging memories to be able to design efficient hardware for such applications. Further, this study addresses thermal challenges associated with such heterogeneous integrated designs. Evaluations are performed to compare various designs and compared against the state-of-the-art. Further, the study proposes path for designing and evaluating future memories and interconnect technologies, providing design insights into various bottlenecks and an evaluation methodology for performing an electrical-thermal system-level co-design. Building upon the CIS and LLM accelerator designs, this dissertation develops a systematic system-technology co-optimization (STCO) methodology for evaluating advanced packaging configurations. The methodology is applied to compare 2.5D interposer, 3D HBM-on-logic, and selective layer transfer (SLT) integration for LLM accelerators across inference and training workloads. Detailed thermal and power delivery analysis is performed for 3D stacked HBM and compute accelerators, examining the trade-offs between memory-on-logic and logic-on-memory configurations. A hybrid design combining elements of both approaches is proposed and shown to achieve favorable thermal profiles while maintaining high memory bandwidth. Finally, a generalized software-hardware co-design framework, NS-AP (NeuroSim for Advanced Packaging), is developed that extends the analysis to arbitrary packaging configurations and workloads. The framework operates at three levels: component, chip, and package, and incorporates physical design, thermal simulation, and power delivery analysis.

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