688637 event 1772490445 1772490536 <![CDATA[Ph.D. Proposal Oral Exam - Kevin Patino-Sosa]]> Title:  Domain-Specific Processor Architecture for High-Density Implantable Brain--Machine Interfaces

Committee:

Dr. Sathe, Advisor

Dr. Raychowdhury, Chair

Dr. Inan

]]> The objective of the proposed research is to design, implement, and validate a domain-specific, heterogeneous System-on-Chip (SoC) for next-generation implantable Brain–Machine Interfaces (BMIs). This work addresses a core conflict in the field: advanced, adaptive algorithms drive up computational demand and power, while thermal safety remains non-negotiable. Therapies such as Phase-Specific Stimulation (PSS) require deterministic, submillisecond end-to-end latency, which increases on-chip power density. In an implant, that density creates localized hotspots that can damage neural tissue and violate safety standards [1, 2]. To resolve this conflict, the proposed architecture co-designs performance and thermal safety as a single problem. The heterogeneous SoC partitions into functionally distinct, asynchronous domains. A real-time, streaming Accelerator (ACC) domain—built from canonical Digital Signal Processing (DSP) accelerators (e.g., Second-Order Section (SOS), Finite Impulse Response (FIR), COordinate Rotation DIgital Computer (CORDIC)) on a dynamic crossbar—executes the “hot loop” with fixed latency. A flexible Central Processing Unit (CPU) domain with a Reduced Instruction Set Computer V (RISC-V) core orchestrates dataflow and runs higher-level stimulation policies. This split also provides a path for Machine Learning (ML) expansion via the integrated Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration (VEGETA) General Matrix–Matrix Multiply (GEMM) accelerator. Two pillars support safety and performance. First, the streaming ACC pipeline uses a fixed, predictable compute cycle budget, decoupling real-time latency from input data. Second, the SoC integrates a complete hardware framework for closed-loop thermal compliance: (i) a sensing plane, a distributed on-die thermal sensor network [3], and (ii) a power/clock control plane, a set of independent power and clock domains that enable perdomain throttling and voltage/frequency scaling. Silicon prototypes validate the architecture. Preliminary 65,nm tapeouts refined the power-domain strategy; one served as a vehicle for a co-authored power-management study [4]. The final design targets Intel 16,nm technology. Performance validation with emulated Analog-to-Digital Converter (ADC) data from the Allen Institute confirms a fixed, low-cycle compute budget (10 ACC cycles + 63 CPU cycles). The result is a silicon-proven, thermally aware platform that exposes the hardware hooks needed for safe, low-latency, energy-efficient closed-loop neuromodulation.

]]> <![CDATA[]]> https://teams.microsoft.com/meet/27628969463407?p=R95Csx8juTkqzsU1hN 434371 1788 102851 1808