686691 event 1764628781 1764628884 <![CDATA[Ph.D. Proposal Oral Exam - Albert Cho]]> Title:  Addressing Memory System Bottlenecks across Various Scale Servers in the Era of CXL

Committee: 

Dr. Daglis, Advisor        

Dr. Qureshi, Chair

Dr. Gavrilovska

]]> The objective of the proposed research is to explore and develop novel memory system architectures that leverage emerging interconnect technologies to overcome the performance bottlenecks exposed in traditional DDR-based server-class processors. With the rising demands in data-intensive applications and manycore scaling, conventional DDR interfaces are increasingly constrained by pin count and bandwidth inefficiencies. At the same time, multi-socket servers exacerbate performance bottlenecks due to Non-Uniform Memory Access (NUMA) effects for remote accesses between sockets. To address these challenges, this work investigates the potential of emerging interconnect technologies like Compute Express Link (CXL) as a foundation for rethinking memory system design. This research makes the following key contributions. First, Coaxial introduces a CXL-only memory interface for throughput-oriented manycore servers, delivering significantly higher bandwidth per pin and improving system performance by mitigating queuing delays. Second, StarNUMA enhances large multi-socket architectures by introducing a centralized CXL-accessible memory pool, effectively addressing the challenge of vagabond pages and reducing remote memory access penalties. Lastly, we investigate opportunities in distributed server systems to leverage CXL memory pool to mitigate bottlenecks in inter-node communication. Together, these contributions demonstrate that with appropriate application of emerging interconnect technologies, memory architectures can substantially improve performance across various scale sized systems, highlighting the transformative role of interconnect innovation in future server designs

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