686525 event 1763544901 1763545025 <![CDATA[Ph.D. Proposal Oral Exam - Nahid Shazon]]> Title:  Exploring Existing and Emerging Memory Technologies for L3 Cache at Advanced Technology Nodes

Committee:

Dr. Naeemi, Advisor

Dr. Davis, Chair

Dr. Khan

]]> The objective of the proposed research is to examine Spin-Orbit Torque Magnetic Random-Access Memory (SOT-MRAM) and advanced interconnect technologies for SRAM, aiming to enable scalable, energy-efficient, and CMOS-compatible memory solutions for future data-centric and AI-driven computing systems. To this end, we present a comprehensive framework to quantify the non-uniformity of the spin current density generated by spin-orbit torque (SOT) in SOT-MRAM. Spin current profile obtained from finite-element simulations and spin drift-diffusion framework indicated that spin current density is considerably diminished at the edges of ferromagnets of the three-terminal conventional SOT-MRAM and does not necessarily follow the conduction current density profile. Afterward, we conducted modeling and benchmarking of two-terminal (2T) SOT-MRAM, which indicates that the common SOT materials that provide only in-plane torque can provide little to no improvement over spin-transfer-torque (STT) MRAM in terms of write energy. However, emerging SOT materials that provide out-of-plane torques with efficiencies as small as 0.1 can result in significant improvements in the write energy for such 2-terminal devices, especially when the magnet lateral dimensions are scaled down to 30 or 20 nm.  A novel 2T-SOT MRAM device is proposed that can increase the path electrons take through the SOT layer, thereby enhancing the generated spin current and the energy efficiency of the device. Our benchmarking results indicate that for our novel SOT-MRAM device, an out-of-plane SOT efficiency of 0.051 for 20 nm wide devices can result in write energies approaching SRAM at the 7nm technology node. At the circuit level, we established a complete SRAM system to evaluate interconnect technologies at the 7 nm scale through a streamlined workflow that includes RTL design, synthesis, floor planning, place-and-route, and clock tree synthesis. We conduct a detailed comparison of interconnect technologies—Copper BKM (industry best-known method), CuThin, Improved Via, and Ruthenium—revealing significant performance differences. Ruthenium-based interconnects demonstrated a 33.4% reduction in energy-delay product and a 20.4% increase in effective frequency when compared to copper. It is also noticed that only improving the via resistances can reduce the EDP by 16.6% from CuBKM. Overall, these initiatives offer a multiscale strategy for enhancing scalable, energy-efficient, and CMOS-compatible memory solutions.

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