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  <title><![CDATA[Ph.D. Proposal Oral Exam - Euichul Chung]]></title>
  <body><![CDATA[<p><strong>Title:&nbsp; </strong><em>Electrical and Thermal Co-design of Interconnects and Microfluidic Cooling Technologies for 2.5D/3D Heterogeneous Integration</em></p><p><strong>Committee:</strong></p><p>Dr. Bakir, Advisor</p><p>Dr. Naeemi, Chair</p><p>Dr. Ansari</p>]]></body>
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      <value><![CDATA[Electrical and Thermal Co-design of Interconnects and Microfluidic Cooling Technologies for 2.5D/3D Heterogeneous Integration]]></value>
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      <value><![CDATA[<p>The objective of the proposed research is the electro-thermal co-design of interconnects and microfluidic cooling technologies to address the challenges of 2.5D and 3D heterogeneous integration in high-performance and quantum computing applications. Two key enabling technologies for such integration are (1) high-density interconnects and (2) effective thermal management solutions, both becoming increasingly critical as system architectures grow in complexity. This study proposes co-designing interconnect and microfluidic cooling technologies to simultaneously meet performance and reliability requirements in advanced packaging platforms. First, we investigate (1) system-level thermal management strategy for a 2.5D high-bandwidth memory (HBM) - graphic processing units (GPUs) integrated with top-side single-phase microfluidic cooling solution, designed to mitigate the challenges associated with multi-die, multi-height configurations and the increasing power density of the dies. Furthermore, as top-side microfluidic cooling technologies approach their limits, we delve into (2) inter-tier microfluidic cooling design for 3D-ICs where TSVs are integrated within a micropin-fin heat sink to enable efficient heat dissipation across stacked dies while maintaining electrical interconnection. Furthermore, we analyze(3) 3D copper compressible microinterconnects (CMIs) as an off-chip interconnect for advanced packaging and explore their potential extension to quantum packaging applications. Building on this preliminary study, the research proposes (1) topology-optimized interlayer cooling with localized TSV architectures to achieve higher bandwidth density while minimizing system temperature, and (2) single- or bi-layer CMIs as off-chip interconnects for quantum computing applications, with a focus on thermal and superconducting CMI technologies.</p>]]></value>
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      <value><![CDATA[2025-11-20T15:30:00-05:00]]></value>
      <value2><![CDATA[2025-11-20T17:30:00-05:00]]></value2>
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      <timezone><![CDATA[America/New_York]]></timezone>
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      <value><![CDATA[Online]]></value>
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        <url>https://teams.microsoft.com/l/meetup-join/19%3ameeting_M2RhZWY3YjQtMzg2MC00NjcwLTg3NDgtNmE2ZWQ3YWQ5Zjli%40thread.v2/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%22c1ec1a51-8fba-4dc9-95c3-88245a28369a%22%7d</url>
        <link_title><![CDATA[Microsoft Teams Meeting link]]></link_title>
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          <item><![CDATA[ECE Ph.D. Proposal Oral Exams]]></item>
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        <tid>1788</tid>
        <value><![CDATA[Other/Miscellaneous]]></value>
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