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  <title><![CDATA[PhD Proposal by Rafael Oliveira  ]]></title>
  <body><![CDATA[<p><strong>Title: End-to-End Support for In-Network Acceleration of Dynamically Chained Parametric Tasks</strong></p><p>&nbsp;</p><p><strong>Rafael Oliveira &nbsp;</strong></p><p>Ph.D. Student in Computer Science &nbsp;</p><p>School of Computer Science &nbsp;</p><p>College of Computing &nbsp;</p><p>Georgia Institute of Technology &nbsp;</p><p>&nbsp;</p><p>Date: Tuesday, September 30th, 2025 &nbsp;</p><p>Time: 3:00pm - 4:30pm ET &nbsp;</p><p>Location: KACB 3100, or<a href="https://gatech.zoom.us/j/98975861466?pwd=YmlMWVU2V1hqL01rbE1KeVZhYnVVQT09" title="https://gatech.zoom.us/j/98975861466?pwd=YmlMWVU2V1hqL01rbE1KeVZhYnVVQT09">&nbsp;Zoom</a></p><p>&nbsp;</p><p>&nbsp;</p><p>&nbsp;</p><p><strong>Committee: &nbsp;</strong></p><p>Dr. Ada Gavrilovska &nbsp;(advisor)&nbsp;– College of Computing, Georgia Institute of Technology &nbsp;</p><p>Dr. Calton Pu&nbsp;– College of Computing, Georgia Institute of Technology &nbsp;</p><p>Dr. Santosh Pande – College of Computing, Georgia Institute of Technology &nbsp;</p><p>Dr. Alex Daglis – College of Computing, Georgia Institute of Technology &nbsp;</p><p>Dr. Hadi Esmaeilzadeh – Computer Science and Engineering, UCSD &nbsp;</p><p>&nbsp;</p><p><strong>Abstract:</strong> Modern cloud infrastructure faces a fundamental inefficiency: while modern software scales through shared resources—from dynamically linked libraries to containerized microservices—SmartNICs allocate dedicated hardware accelerators per tenant,&nbsp;evoking the pre-DLL era where common functions were duplicated in every program. This wastes precious hardware resources in multi-tenant environments where applications often need the same computations (AES encryption, Kalman filters) with different parameters.</p><p>This thesis introduces parametric Compute Unit (CU) sharing—enabling multiple tenants to share hardware accelerators just as software shares libraries. The key challenge is managing parameters at line rate: unlike software's flexible memory, hardware requires deterministic, cycle-accurate parameter delivery across dynamically composed processing chains.</p><p>We present three systems that collectively solve this challenge: Vazado&nbsp;enables dynamic chaining of CUs with incompatible signatures through hardware-compiler co-design, achieving 13.19× energy efficiency over 48-core CPUs while using just 10% of FPGA resources. ErdTree&nbsp;introduces hierarchical topic trees that reduce memory footprints by 52% through automatic parameter deduplication and hardware-friendly FIFO caching. COMPREX&nbsp;accelerates NIC-CPU transfers 7× through domain-specific compression.</p><p>Together, these systems demonstrate that efficient multi-tenant acceleration is achievable without sacrificing programmability—enabling SmartNICs to finally deliver on their promise of scalable, shared acceleration for cloud infrastructure.</p>]]></body>
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      <value><![CDATA[2025-09-30T15:00:00-04:00]]></value>
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