His paper, “Heterogeneous Integration Enabled by 3D Stitch-Chips," recently won the Best Paper Award in the Advanced Packaging Technologies from the IEEE Transactions on Components, Packaging and Manufacturing Technology, a premier package design publication.

Traditional chip interconnect methods like wire-bonding or flip-chip mounting either struggle with signal integrity at high frequencies or require complex fabrication steps.

The paper introduces a new interconnect technology called the 3D Stitch-Chip (3DSC), which offers a novel solution to the limitations of traditional interconnection methods such as wire bonding, die-embedding, and flip-chip bonding. Existing methods can be bulky, hard to manufacture, or cause issues with signal quality, especially when dealing with fast, high-frequency signals used in modern electronics.

3DSC avoids these problems by using a special structure that includes vertical channels and lateral connectors to link chips together. This allows the chips to be mounted face-up, without digging cavities, and helps keep signals clear even at very high speeds. This new method was successfully demonstrated for Ka-band frequencies (26-40 gigahertz), which are used in cutting-edge wireless and radar systems. Its modular design makes it especially useful for building complex systems that combine many different chips in a compact space.

He, along with his co-authors— Ph.D. students Zhonghao Zhang and Geyu Yan, and Georgia Tech Research Institute senior research engineer Paul K. Jo—conducted the research under the guidance of professor Muhannad S. Bakir, as part of the Integrated 3D Systems Group.

The work contributes to the group’s broader mission to rethink packaging architectures for heterogeneous integration, enabling future radio frequency systems to be smaller, faster, and more efficient.

Oh, Zhang, Jo, and Bakir will accept the award during the 75th Electronic Components and Technology Conference.