681762 event 1744631933 1744632024 <![CDATA[Ph.D. Proposal Oral Exam - Wei Chun Wang]]> Title:  Energy and Area Efficient Analog Computing-in-Memory Systems: From Device-Circuit Co-Design to RF Signal Processing Applications

Committee:

Dr. Mukhopadhyay, Advisor

Dr. Datta, Chair

Dr. Romberg

]]> This research explores advanced sensor array technologies, addressing the challenges of energy consumption and data processing in next-generation high-bandwidth RF arrays. It introduces an analog computing-in-memory (ACIM) framework utilizing advanced mixed-mode matrix multiplication to extract low-dimensional features directly from high-dimensional analog inputs, significantly reducing data rates while maintaining accuracy. At the circuit level, an SRAM-based ACIM architecture in 28nm CMOS is developed to perform current-domain multiply-and-accumulate (MAC) operations without requiring on-chip capacitors. Additionally, a separate study enhances ACIM design using 1-transistor Fe-FinFET cells with FinFET-based peripherals, improving linearity, reducing variations, and increasing power and area efficiency. Another research effort focuses on FinFET SRAM-based ACIM at cryogenic temperatures, leveraging higher on-to-off current ratios and improved transconductance characteristics to enhance power efficiency and reduce energy-delay product (EDP). At the system level, an adaptive ACIM framework incorporating a modified Oja’s algorithm dynamically optimizes the compression matrix based on real-time signal subspace estimates. This approach successfully compresses signals from 1024 antenna elements into 64 channels while maintaining accuracy, marking a significant step toward practical, power-efficient, high-resolution sensing platforms.

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