678285 event 1731056493 1731056588 <![CDATA[Ph.D. Proposal Oral Exam - Ashita Victor]]> Title:  Wafer-scale Chiplet Reconstitution Technology for High-density Heterogeneous Integration

Committee: 

Dr. Bakir, Advisor 

Dr. Ansari, Chair

Dr. Mukhopadhyay

]]> The objective of the proposed research is to enable high-density heterogeneous integration (HI) of chiplets using wafer-scale packaging techniques. As the number of chiplets in a package increases, it becomes more challenging to achieve near-monolithic integration. To tackle this challenge, we propose a chiplet reconstitution technology that leverages low-temperature silicon dioxide (SiO2) to encapsulate an array of closely spaced chiplets to form a reconstituted tier. This approach allows for post-processing on the chiplets at a wafer scale. These chiplet tiers can potentially be stacked in 3D to enable high-density chiplet integration. We have developed fabrication testbeds to demonstrate this proposed packaging solution. The fabrication testbed comprises of a dense array of ultra-thin passive chiplets which are 10 – 30 um-thick with chiplet-to-chiplet gaps ranging from 10 – 60 um.  To ensure complete chiplet encapsulation using silicon dioxide and achieve near-monolithic integration, we conducted a study to determine the minimum chiplet-to-chiplet gap required for a specific chiplet thickness. Additionally, we discuss methods for transferring extremely thin (< 35 um) reconstituted-SiO2 tiers for post-processing. Furthermore, we demonstrate the ability to fabricate high-density vertical interconnects (through-oxide-vias) with via diameters ranging from 2 – 5 um and pitches ranging from 4 – 15 um, resulting in a >10x increase in vertical interconnect density compared to conventional epoxy-based fan-out wafer-level packages. We also present a testbed showcasing fine-pitch lateral interconnects with a line/spacing of 2.8/2 um. Future work will involve demonstrating the proposed reconstitution technology for multi-height chiplet assemblies. We also aim to demonstrate the ability to integrate the SiO2-based reconstituted chiplet tiers in 3D. Finally, we plan to evaluate the die-to-die signaling for this packaging solution using compact circuit models and benchmark it against state-of-the-art 2.5D/3D HI architectures.

]]> <![CDATA[]]> https://teams.microsoft.com/l/meetup-join/19%3ameeting_NzUyMWQ3MTUtNzIwOC00NjFkLThkZmQtMWJlYWE4OTkwNGY5%40thread.v2/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%2205646042-9e29-48aa-bb0c-c2cadb331749%22%7d 434371 1788 102851 1808