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  <title><![CDATA[PhD Defense by Matthew Whitlock]]></title>
  <body><![CDATA[<p><strong>Title:&nbsp;</strong>Designing and Automating Asynchronous, Localized, Multi-Level Fault-Tolerance at the Application Level</p><p>&nbsp;</p><p><strong>Date:&nbsp;</strong>Thursday, August 15, 2024</p><p><strong>Time:</strong>&nbsp;3pm - 5pm EST</p><p><strong>Location:&nbsp;</strong>Klaus 3402</p><p><strong>Remote</strong>: via <a href="https://teams.microsoft.com/l/meetup-join/19%3ameeting_MDI0MGIyMWQtNzhkNC00MzFmLTg3NDItM2JjMWQ2MmI5YWZh%40thread.v2/0?context=%7b%22Tid%22%3a%22482198bb-ae7b-4b25-8b7a-6d7f32faa083%22%2c%22Oid%22%3a%221ca2054b-a945-4131-9ad7-f3552a880051%22%7d">Teams</a></p><p>&nbsp;</p><p><strong>Matthew Whitlock</strong></p><p>Ph.D. Candidate in Computer Science</p><p>School of Computer Science</p><p>College of Computing</p><p>Georgia Institute of Technology</p><p>&nbsp;</p><p><strong>Committee:</strong></p><p>Dr. Vivek Sarkar (Advisor) - School of Computer Science, Georgia Institute&nbsp;of Technology</p><p>Dr. Keita Teranishi - Advanced Computing Systems Research Section, Oak Ridge National Laboratories</p><p>Dr. Ada Gavrilovska - School of Computer Science, Georgia Institute of&nbsp;Technology</p><p>Dr. Umakishore Ramachandran - School of Computer Science, Georgia Institute&nbsp;of Technology</p><p>Dr. Tom Conte - School of Computer Science, Georgia Institute of Technology</p><p>&nbsp;</p><p><strong>Abstract</strong></p><p>Moore's law is dead or dying, but Rock's law of doubling costs for semiconductor fabrication is still going strong. It is becoming more expensive to meet ever-growing compute demands, and the general public is expressing growing concerns about the environmental impact of extreme-scale computing. Consequently, researchers in fields like machine learning and embedded computing are exploring reduced-reliability computing.</p><p>&nbsp;</p><p>Supercomputing facilities, however, are struggling to maintain high-reliability hardware to support the inefficient and unscalable global checkpoint/restart (C/R) mechanisms that most scientific computing applications continue to rely on. The performance cost of C/R is rising faster than the performance of leading supercomputers. Applications' fault-tolerance must scale against higher parallelism and reduced hardware reliability for HPC to continue scaling while reigning in its environmental footprint. To avoid the exponential growth of C/R overheads, applications must localize the cost of hardware faults. Further, fault tolerance must be flexible to application-specific refinements while managing application developers' reticence to implement complex resilience code.&nbsp;</p><p>&nbsp;</p><p>We describe a layer-based resilience taxonomy that exposes the imperative configurability mechanisms to make fault-tolerance tools that can flexibly combine to utilize general application- and platform- tailored fault recovery. We prove this by extending contemporary resilience tools to enable flexible, easy-to-implement online recovery into applications with a multi-layered approach. Next, we define the key requirements of localized recovery by creating a general analytical model for local recovery. We prove that recovery can be localized using modern User-Level Fault Tolerance (ULFM) MPI features despite ULFM's collective recovery constraints. Finally, we prove that asynchrony via task-based parallelism can mitigate the non-local costs of recovery for applications which cannot strictly meet the requirements for localized recovery.</p><p>&nbsp;</p><p>These works build the path for HPC to maintain environmental accountability, meet growing compute demands, and benefit from novel upcoming hardware trends.</p>]]></body>
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