675678 event 1722292375 1722373736 <![CDATA[Ph.D. Proposal Oral Exam - Diego Pena Colaiocco]]> Title:  Formulation and Efficient Implementation of Optimization Methods and Programs for Enhancing the Performance of Digital Integrated Circuits

Committee: 

Dr. Sathe, Advisor 

Dr. Romberg, Chair

Dr. Raychowdhury

]]> The objective of the proposed research is to enhance the performance of digital integrated circuits through the formulation and efficient implementation of optimization methods and programs. The proposed work can be divided in two main efforts. The first relating to baseband processors for optimal mm-Wave beamforming (two different architectures are proposed). The second being the estimation of worst-case Vdd droops on Power Delivery Systems (PDSs) at design time, through a numerical optimization problem. Modern mm-Wave beamformers are usually implemented in the analog domain, because of the high energy consumption demanded by fully digital beamformers. However, their performance is not adequate when some transmitters are in motion. In this proposal, we describe two baseband processors for this scenario. One is the first known implementation of run-time optimal mm-Wave beamforming that maximizes signal to interference plus noise ratio (SINR) in the presence of multiple interferers in motion, with a stationary signal of interest. The second adds signal tracking capabilities, enabling optimal beamforming even when the signal of interest is in motion. It also mitigates beam squinting by using Orthogonal Frequency Division Multiplexing (OFDM). Accurate determination of worst-case droop at design time is critical; PDS designers depend on it to make the trade-offs necessary to optimize overall system efficiency. Even though modern systems in package continue to employ more sophisticated PDS architectures, conventional design methodologies do not consider interactions across different voltage domains and with the board and socket, nor architectural constraints on load current profiles. The proposed research fills this gap by introducing a SPICE-accurate framework based on numerical optimization to estimate the worst-case voltage droop of PDSs for Systems-on-Chip.

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